Table of Contents
Advertisement
3.
Input capture register GR (ICRGR)
Bit:
7
ICRGR7
Initial value:
0
Read/Write:
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2ø
ICRGR is initialized to H'00 upon reset.
4. Timer mode register G (TMG)
7
Bit:
OVFH
Initial value:
0
Read/Write:
R/W*
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
6
5
ICRGR6
ICRGR5
0
0
R
R
(when the noise canceler is not used).
SUB
6
5
OVFL
OVIE
0
0
R/W*
R/W
4
3
ICRGR4
ICRGR3
0
0
R
R
4
3
IIEGS
CCLR1
0
0
R/W
R/W
216
2
1
ICRGR2
ICRGR1
0
0
R
R
2
1
CCLR0
CKS1
0
0
R/W
R/W
0
ICRGR0
0
R
0
CKS0
0
R/W
Advertisement
Table of Contents
