Texas Instruments TMS320C6748 Manual page 201

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Table 6-100. Timing Requirements for EMAC MII Receive 10/100 Mbit/s
NO.
1 t Setup time, receive selected signals valid before MII_RXCLK high
su(MRXD-MII_RXCLKH)
2 t Hold time, receive selected signals valid after MII_RXCLK high
h(MII_RXCLKH-MRXD)
(1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.
MII_RXCLK (Input)
MII_RXD[3]-MII_RXD[0],
MII_RXDV, MII_RXER (Inputs)
Table 6-101. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
NO.
t
d(MII_TXCLKH-
1 Delay time, MII_TXCLK high to transmit selected signals valid
MTXD)
(1) Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.
MII_TCLK (Input)
MII_TXD[3]-MII_TXD[0],
MII_TXEN (Outputs)
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Figure 6-49. EMAC Receive Interface Timing
(1)
10/100 Mbit/s (see
PARAMETER
Figure 6-50. EMAC Transmit Interface Timing
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SPRS590G – JUNE 2009 – REVISED JANUARY 2017
(1)
1
2
Figure 6-50)
1.3V, 1.2V,
MIN
2
1
Peripheral Information and Electrical Specifications
TMS320C6748
TMS320C6748
(see Figure 6-49)
1.3V, 1.2V, 1.1V,
1.0V
UNIT
MIN MAX
8 ns
8 ns
1.0V
1.1V
UNIT
MAX MIN MAX
25 2 32 ns
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