Texas Instruments TMS320C6748 Manual page 168

Fixed- and floating-point dsp
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TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
NO.
Delay from SPI0_SCS active to
22
t
d(SCS_SPC)M
first SPI0_CLK
Delay from assertion of SPI0_ENA
23
t
d(ENA_SPC)M
low to first SPI0_CLK edge.
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
NO.
PARAMETER
Delay from final SPI0_CLK edge
24
t
d(SPC_ENAH)S
to slave deasserting SPI0_ENA.
(1) These parameters are in addition to the general timings for SPI slave modes
(2) P = SYSCLK2 period; M = t
(SPI master bit clock period)
c(SPC)M
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
168
Peripheral Information and Electrical Specifications
Table 6-72. Additional SPI0 Master Timings, 5-Pin Option
PARAMETER
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
(10)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Table 6-73. Additional SPI0 Slave Timings, 4-Pin Enable Option
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
– 0.5M+1.5P-3
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
– 0.5M+1.5P-3
from SPI0_CLK rising
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(1)(2)(3)
1.3V, 1.2V
MIN
MAX
2P-2
0.5M+2P-2
0.5M+2P-2
2P-2
0.5M+2P-2
0.5M+2P-2
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
1.3V, 1.2V
MIN
MAX
MIN
1.5P-3
2.5P+17.5
1.5P-3
– 0.5M+2.5P+17.5
– 0.5M+1.5P-3
1.5P-3
2.5P+17.5
1.5P-3
– 0.5+2.5P+17.5
– 0.5M+1.5P-3
(Table
6-69).
TMS320C6748
(continued)
1.1V
1.0V
MIN
MAX
MIN
2P-2
2P-3
0.5M+2P-3
2P-2
2P-3
0.5M+2P-3
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
(1) (2) (3)
1.1V
1.0V
MAX
MIN
2.5P+20
1.5P-3
– 0.5M+2.5P+20
– 0.5M+1.5P-3
2.5P+20
1.5P-3
– 0.5+2.5P+20
– 0.5M+1.5P-3
Copyright © 2009–2017, Texas Instruments Incorporated
www.ti.com
UNIT
MAX
ns
3P+6
0.5M+3P+6
ns
3P+6
0.5M+3P+6
UNIT
MAX
2.5P+27
– 0.5M+2.5P+27
ns
2.5P+27
– 0.5+2.5P+27

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