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6.9
Enhanced Direct Memory Access Controller (EDMA3)
The EDMA3 controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.
6.9.1 EDMA3 Channel Synchronization Events
Each EDMA3 channel controller supports up to 32 channels which service peripherals and memory.
Table 6-12
lists the source of the EDMA3 synchronization events associated with each of the
programmable EDMA channels.
Event
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Copyright © 2009–2017, Texas Instruments Incorporated
Table 6-12. EDMA Synchronization Events
EDMA3 Channel Controller 0
Event Name / Source
McASP0 Receive
McASP0 Transmit
McBSP0 Receive
McBSP0 Transmit
McBSP1 Receive
McBSP1 Transmit
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
UART0 Transmit
Timer64P0 Event Out 12
Timer64P0 Event Out 34
UART1 Receive
UART1 Transmit
SPI0 Receive
SPI0 Transmit
EDMA3 Channel Controller 1
Event Name / Source
Timer64P2 Compare Event 0
Timer64P2 Compare Event 1
Timer64P2 Compare Event 2
Timer64P2 Compare Event 3
Timer64P2 Compare Event 4
Timer64P2 Compare Event 5
Timer64P2 Compare Event 6
Timer64P2 Compare Event 7
Timer64P3 Compare Event 0
Timer64P3 Compare Event 1
Timer64P3 Compare Event 2
Timer64P3 Compare Event 3
Timer64P3 Compare Event 4
Timer64P3 Compare Event 5
Timer64P3 Compare Event 6
Timer64P3 Compare Event 7
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Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Peripheral Information and Electrical Specifications
TMS320C6748
TMS320C6748
Event Name / Source
MMCSD0 Receive
MMCSD0 Transmit
SPI1 Receive
SPI1 Transmit
PRU_EVTOUT6
PRU_EVTOUT7
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
I2C0 Transmit
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART2 Transmit
Event Name / Source
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
GPIO Bank 8 Interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Timer64P2 Event Out 12
Timer64P2 Event Out 34
Timer64P3 Event Out 12
Timer64P3 Event Out 34
MMCSD1 Receive
MMCSD1 Transmit
Reserved
Reserved
101
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