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TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
3 Device Comparison
3.1
Device Characteristics
Table 3-1
provides an overview of the device. The table shows significant features of the device, including
the capacity of on-chip RAM, peripherals, and the package type with pin count.
HARDWARE FEATURES
DDR2/mDDR Memory Controller
EMIFA
Flash Card Interface
EDMA3
Timers
UART
SPI
2
I
C
Peripherals
Multichannel Audio Serial Port [McASP]
Not all peripherals pins
Multichannel Buffered Serial Port [McBSP]
are available at the
10/100 Ethernet MAC with Management Data I/O
same time (for more
detail, see the Device
eHRPWM
Configurations section).
eCAP
UHPI
USB 2.0 (USB0)
USB 1.1 (USB1)
General-Purpose Input/Output Port
LCD Controller
SATA Controller
Universal Parallel Port (uPP)
Video Port Interface (VPIF)
PRU Subsystem (PRUSS)
Size (Bytes)
On-Chip Memory
Organization
Security
Secure Boot
C674x CPU ID + CPU
Control Status Register (CSR.[31:16])
Rev ID
C674x Megamodule
Revision ID Register (MM_REVID[15:0])
Revision
JTAG BSDL_ID
DEVIDR0 Register
CPU Frequency
MHz
8
Device Comparison
Table 3-1. Characteristics of C6748
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TMS320C6748
C6748
DDR2, 16-bit bus width, up to 156 MHz
Mobile DDR, 16-bit bus width, up to 150 MHz
Asynchronous (8/16-bit bus width) RAM, Flash,
16-bit SDRAM, NOR, NAND
2 MMC and SD cards supported
64 independent channels, 16 QDMA channels,
2 channel controllers, 3 transfer controllers
4 64-Bit General Purpose (each configurable as 2 separate
32-bit timers, one configurable as Watch Dog)
3 (each with RTS and CTS flow control)
2 (Each with one hardware chip select)
2 (both Master/Slave)
1 (each with transmit/receive, FIFO buffer, 16 serializers)
2 (each with transmit/receive, FIFO buffer, 16)
1 (MII or RMII Interface)
4 Single Edge, 4 Dual Edge Symmetric, or
2 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
1 (16-bit multiplexed address/data)
High-Speed OTG Controller with on-chip OTG PHY
Full-Speed OHCI (as host) with on-chip PHY
9 banks of 16-bit
1
1 (Supports both SATA I and SATAII)
1
1 (video in and video out)
2 Programmable PRU Cores
448KB RAM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to EDMA3 and
other peripherals.
ADDITIONAL MEMORY
128KB RAM
TI Basic Secure Boot
0x1400
0x0000
see
Section
6.34.4.1, JTAG Peripheral Register Description
674x DSP 375 MHz (1.2V) or 456 MHz (1.3V)
Copyright © 2009–2017, Texas Instruments Incorporated
www.ti.com
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