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TMS320C6743
Texas Instruments TMS320C6743 Manuals
Manuals and User Guides for Texas Instruments TMS320C6743. We have
2
Texas Instruments TMS320C6743 manuals available for free PDF download: Technical Reference Manual, User Manual
Texas Instruments TMS320C6743 Technical Reference Manual (1158 pages)
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 6 MB
Table of Contents
Table of Contents
2
About this Manual
51
Notational Conventions
51
Related Documentation from Texas Instruments
51
Preface
51
Read this First
51
Overview
52
Introduction
53
Block Diagram
53
DSP Subsystem
53
DMA Subsystem
53
TMS320C6743 DSP Block Diagram
53
DSP Subsystem
54
Introduction
55
Tms320C674X Megamodule Block Diagram
55
Peripherals
55
Tms320C674X Megamodule
56
Internal Memory Controllers
56
Internal Peripherals
56
DSP Interrupt Map
56
Memory Map
60
DSP Internal Memory
60
External Memory
60
Advanced Event Triggering (AET)
61
System Interconnect
62
Introduction
63
TMS320C6743 DSP System Interconnect Matrix
63
System Interconnect Block Diagram
64
System Memory
65
Introduction
66
DSP Memories
66
External Memories
66
Internal Peripherals
66
Peripherals
66
Memory Protection Unit (MPU)
67
Introduction
68
Purpose of the MPU
68
Features
68
Block Diagram
68
MPU Block Diagram
68
MPU Default Configuration
69
Architecture
69
Privilege Levels
69
MPU Memory Regions
69
MPU2 Default Configuration
69
Device Master Settings
69
Memory Protection Ranges
70
Permission Structures
70
Permission Fields
70
Protection Check
71
Request Type Access Controls
71
DSP L1/L2 Cache Controller Accesses
72
MPU Register Protection
72
Invalid Accesses and Exceptions
72
Reset Considerations
72
Interrupt Support
72
Emulation Considerations
73
MPU Registers
73
MPU_BOOTCFG_ERR Interrupt Sources
73
Memory Protection Unit 2 (MPU2) Registers
73
Revision Identification Register (REVID)
74
Revision ID Register (REVID)
74
Revision ID Register (REVID) Field Descriptions
74
Configuration Register (CONFIG)
75
Configuration Register (CONFIG) Field Descriptions
75
Interrupt Raw Status/Set Register (IRAWSTAT)
76
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
76
Interrupt Enable Status/Clear Register (IENSTAT)
77
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
77
Interrupt Enable Set Register (IENSET)
78
Interrupt Enable Clear Register (IENCLR)
78
Interrupt Enable Set Register (IENSET) Field Descriptions
78
Interrupt Enable Clear Register (IENCLR) Field Descriptions
78
Fixed Range Start Address Register (FXD_MPSAR)
79
Fixed Range End Address Register (FXD_MPEAR)
79
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
80
Programmable Range N Start Address Registers (Progn_Mpsar)
81
Programmable Range N End Address Registers (Progn_Mpear)
82
Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
83
Fault Address Register (FLTADDRR)
84
Fault Address Register (FLTADDRR) Field Descriptions
84
Fault Status Register (FLTSTAT)
85
Fault Status Register (FLTSTAT) Field Descriptions
85
Fault Clear Register (FLTCLR)
86
Fault Clear Register (FLTCLR) Field Descriptions
86
Device Clocking
87
Overview
88
Device Clock Inputs
88
System Clock Domains
88
Frequency Flexibility
89
Overall Clocking Diagram
89
Example PLL Frequencies
90
Peripheral Clocking
91
EMIFB Clocking
91
EMIFB Clocking Diagram
92
EMIFB MCLK Frequencies
92
EMIFA Clocking
93
EMIFA Clocking Diagram
93
EMIFA Frequencies
93
EMAC Clocking
94
EMAC Clocking Diagram
94
EMAC Reference Clock Frequencies
95
I/O Domains
96
Phase-Locked Loop Controller (PLLC)
97
Introduction
98
PLL0 Control
98
PLL0 Structure
99
Device Clock Generation
100
System PLLC0 Output Clocks
100
Steps for Changing PLL0 Domain Frequency
101
Locking/Unlocking PLL Register Access
102
PLLC Registers
103
PLL Controller (PLLC) Registers
103
Revision Identification Register (REVID)
104
Reset Type Status Register (RSTYPE)
104
Revision Identification Register (REVID) Field Descriptions
104
Reset Type Status Register (RSTYPE) Field Descriptions
104
PLL Control Register (PLLCTL)
105
PLL Control Register (PLLCTL) Field Descriptions
105
PLL Multiplier Control Register (PLLM)
106
PLL Pre-Divider Control Register (PREDIV)
106
PLL Multiplier Control Register (PLLM) Field Descriptions
106
PLL Pre-Divider Control Register (PREDIV) Field Descriptions
106
PLL Controller Divider 1 Register (PLLDIV1)
107
PLL Controller Divider 2 Register (PLLDIV2)
107
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
107
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
107
PLL Controller Divider 3 Register (PLLDIV3)
108
PLL Controller Divider 4 Register (PLLDIV4)
108
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
108
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
108
PLL Controller Divider 5 Register (PLLDIV5)
109
PLL Controller Divider 6 Register (PLLDIV6)
109
PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
109
PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions
109
PLL Controller Divider 7 Register (PLLDIV7)
110
PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions
110
PLL Post-Divider Control Register (POSTDIV)
111
PLL Controller Command Register (PLLCMD)
111
PLL Post-Divider Control Register (POSTDIV) Field Descriptions
111
PLL Controller Command Register (PLLCMD) Field Descriptions
111
PLL Controller Status Register (PLLSTAT)
112
PLL Controller Status Register (PLLSTAT) Field Descriptions
112
PLL Controller Clock Align Control Register (ALNCTL)
113
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
113
PLLDIV Ratio Change Status Register (DCHANGE)
114
PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
114
Clock Enable Control Register (CKEN)
115
Clock Enable Control Register (CKEN) Field Descriptions
115
Clock Status Register (CKSTAT)
116
Clock Status Register (CKSTAT) Field Descriptions
116
SYSCLK Status Register (SYSTAT)
117
SYSCLK Status Register (SYSTAT) Field Descriptions
117
Emulation Performance Counter 0 Register (EMUCNT0)
118
Emulation Performance Counter 1 Register (EMUCNT1)
118
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
118
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
118
Power and Sleep Controller (PSC)
119
Introduction
120
Power Domain and Module Topology
120
SPRUH90B - March
120
Submit Documentation Feedback
120
PSC0 Default Module Configuration
120
Module States
120
PSC1 Default Module Configuration
121
Power Domain States
122
Module States
122
Executing State Transitions
124
Power Domain State Transitions
124
Module State Transitions
124
Icepick Emulation Support in the PSC
125
PSC Interrupts
125
Interrupt Events
125
Icepick Emulation Commands
125
PSC Interrupt Events
125
Interrupt Registers
126
Interrupt Handling
127
PSC Registers
128
Power and Sleep Controller 0 (PSC0) Registers
128
Power and Sleep Controller 1 (PSC1) Registers
128
Revision Identification Register (REVID)
129
Interrupt Evaluation Register (INTEVAL)
129
Revision Identification Register (REVID) Field Descriptions
129
Interrupt Evaluation Register (INTEVAL) Field Descriptions
129
PSC0 Module Error Pending Register 0 (Modules 0-15) (MERRPR0)
130
PSC1 Module Error Pending Register 0 (Modules 0-31) (MERRPR0)
130
PSC0 Module Error Pending Register 0 (MERRPR0)
130
PSC1 Module Error Pending Register 0 (MERRPR0)
130
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
130
PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0)
131
PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0)
131
PSC0 Module Error Clear Register 0 (MERRCR0)
131
PSC1 Module Error Clear Register 0 (MERRCR0)
131
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
131
Power Error Pending Register (PERRPR)
132
Power Error Clear Register (PERRCR)
132
Power Error Pending Register (PERRPR) Field Descriptions
132
Power Error Clear Register (PERRCR) Field Descriptions
132
Power Domain Transition Command Register (PTCMD)
133
Power Domain Transition Command Register (PTCMD) Field Descriptions
133
Power Domain Transition Status Register (PTSTAT)
134
Power Domain Transition Status Register (PTSTAT) Field Descriptions
134
Power Domain 0 Status Register (PDSTAT0)
135
Power Domain 0 Status Register (PDSTAT0) Field Descriptions
135
Power Domain 1 Status Register (PDSTAT1)
136
Power Domain 1 Status Register (PDSTAT1) Field Descriptions
136
Power Domain 0 Control Register (PDCTL0)
137
Power Domain 0 Control Register (PDCTL0) Field Descriptions
137
Power Domain 1 Control Register (PDCTL1)
138
Power Domain 1 Control Register (PDCTL1) Field Descriptions
138
Power Domain 0 Configuration Register (PDCFG0)
139
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
139
Power Domain 1 Configuration Register (PDCFG1)
140
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
140
Module Status N Register (Mdstatn)
141
Module Status N Register (Mdstatn) Field Descriptions
141
PSC0 Module Control N Register (Modules 0-15) (Mdctln)
142
PSC0 Module Control N Register (Mdctln)
142
PSC0 Module Control N Register (Mdctln) Field Descriptions
142
PSC1 Module Control N Register (Modules 0-31) (Mdctln)
143
PSC1 Module Control N Register (Mdctln)
143
PSC1 Module Control N Register (Mdctln) Field Descriptions
143
Power Management
144
Introduction
145
Power Consumption Overview
145
PSC and PLLC Overview
145
Features
146
Power Management Features
146
Clock Management
147
Module Clock ON/OFF
147
Module Clock Frequency Scaling
147
PLL Bypass and Power down
147
DSP Sleep Mode Management
148
C674X DSP CPU Sleep Mode
148
C674X Megamodule Sleep Mode
148
Additional Peripheral Power Management Considerations
148
EMIFB Memory Clock Gating
148
System Configuration (SYSCFG) Module
149
Introduction
150
Protection
151
Requirements to Access SYSCFG Registers
151
System Configuration (SYSCFG) Module Register Access
151
Master Priority Control
152
Master Ids
152
Interrupt Support
153
Interrupt Events and Requests
153
Interrupt Multiplexing
153
Host-DSP Communication Interrupts
153
Default Master Priority
153
SYSCFG Registers
154
System Configuration Module (SYSCFG) Registers
154
Revision Identification Register (REVID)
155
Device Identification Register 0 (DEVIDR0)
155
Revision Identification Register (REVID) Field Descriptions
155
Device Identification Register 0 (DEVIDR0) Field Descriptions
155
Boot Configuration Register (BOOTCFG)
156
Silicon Revision Identification Register (CHIPREVID)
156
Boot Configuration Register (BOOTCFG) Field Descriptions
156
Silicon Revision Identification Register (CHIPREVID) Field Descriptions
156
Kick Registers (KICK0R-KICK1R)
157
Kick 0 Register (KICK0R)
157
Kick 1 Register (KICK1R)
157
Kick 0 Register (KICK0R) Field Descriptions
157
Kick 1 Register (KICK1R) Field Descriptions
157
Host 1 Configuration Register (HOST1CFG)
158
Host 1 Configuration Register (HOST1CFG) Field Descriptions
158
Interrupt Registers
159
Interrupt Raw Status/Set Register (IRAWSTAT)
159
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
159
Interrupt Enable Status/Clear Register (IENSTAT)
160
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
160
Interrupt Enable Register (IENSET)
161
Interrupt Enable Clear Register (IENCLR)
161
Interrupt Enable Register (IENSET) Field Descriptions
161
Interrupt Enable Clear Register (IENCLR) Field Descriptions
161
Fault Registers
162
End of Interrupt Register (EOI)
162
Fault Address Register (FLTADDRR)
162
End of Interrupt Register (EOI) Field Descriptions
162
Fault Address Register (FLTADDRR) Field Descriptions
162
Fault Status Register (FLTSTAT)
163
Fault Status Register (FLTSTAT) Field Descriptions
163
Master Priority Registers (MSTPRI0-MSTPRI2)
164
Master Priority 0 Register (MSTPRI0)
164
Master Priority 0 Register (MSTPRI0) Field Descriptions
164
Master Priority 1 Register (MSTPRI1)
165
Master Priority 1 Register (MSTPRI1) Field Descriptions
165
Master Priority 2 Register (MSTPRI2)
166
Master Priority 2 Register (MSTPRI2) Field Descriptions
166
Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
167
Pin Multiplexing Control 0 Register (PINMUX0)
167
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
167
Pin Multiplexing Control 1 Register (PINMUX1)
169
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
169
Pin Multiplexing Control 2 Register (PINMUX2)
171
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
171
Pin Multiplexing Control 3 Register (PINMUX3)
173
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
173
Pin Multiplexing Control 4 Register (PINMUX4)
174
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
174
Pin Multiplexing Control 5 Register (PINMUX5)
175
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
175
Pin Multiplexing Control 6 Register (PINMUX6)
177
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
177
Pin Multiplexing Control 7 Register (PINMUX7)
179
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
179
Pin Multiplexing Control 8 Register (PINMUX8)
181
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
181
Pin Multiplexing Control 9 Register (PINMUX9)
183
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
183
Pin Multiplexing Control 10 Register (PINMUX10)
185
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
185
Pin Multiplexing Control 11 Register (PINMUX11)
187
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
187
Pin Multiplexing Control 12 Register (PINMUX12)
189
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
189
Pin Multiplexing Control 13 Register (PINMUX13)
191
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
191
Pin Multiplexing Control 14 Register (PINMUX14)
193
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
193
Pin Multiplexing Control 15 Register (PINMUX15)
195
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
195
Pin Multiplexing Control 16 Register (PINMUX16)
197
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
197
Pin Multiplexing Control 17 Register (PINMUX17)
199
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
199
Pin Multiplexing Control 18 Register (PINMUX18)
201
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
201
Pin Multiplexing Control 19 Register (PINMUX19)
202
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
202
Suspend Source Register (SUSPSRC)
203
Suspend Source Register (SUSPSRC) Field Descriptions
203
Chip Signal Register (CHIPSIG)
205
Chip Signal Register (CHIPSIG) Field Descriptions
205
Chip Signal Clear Register (CHIPSIG_CLR)
206
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
206
Chip Configuration 0 Register (CFGCHIP0)
207
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
207
Chip Configuration 1 Register (CFGCHIP1)
208
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
208
Chip Configuration 3 Register (CFGCHIP3)
211
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
211
Chip Configuration 4 Register (CFGCHIP4)
212
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
212
Boot Considerations
213
Introduction
214
Programmable Real-Time Unit Subsystem (PRUSS)
215
Enhanced Capture (Ecap) Module
216
Introduction
217
Purpose of the Peripheral
217
Features
217
Architecture
218
Multiple Ecap Modules
218
Capture and APWM Operating Mode
219
Capture and APWM Modes of Operation
219
Capture Mode Description
220
Capture Function Diagram
220
Event Prescale Control
221
Prescale Function Waveforms
221
Continuous/One-Shot Block Diagram
222
Counter and Synchronization Block Diagram
223
Interrupts in Ecap Module
225
PWM Waveform Details of APWM Mode Operation
226
Applications
227
Absolute Time-Stamp Operation Rising Edge Trigger Example
228
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
228
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
229
Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
230
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
230
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
231
Time Difference (Delta) Operation Rising Edge Trigger Example
232
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
232
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
233
Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
234
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
234
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
235
Application of the APWM Mode
236
PWM Waveform Details of APWM Mode Operation
236
ECAP Initialization for APWM Mode
237
Multichannel PWM Example Using 4 Ecap Modules
238
ECAP1 Initialization for Multichannel PWM Generation with Synchronization
239
ECAP2 Initialization for Multichannel PWM Generation with Synchronization
239
ECAP3 Initialization for Multichannel PWM Generation with Synchronization
239
ECAP4 Initialization for Multichannel PWM Generation with Synchronization
239
Multiphase (Channel) Interleaved PWM Example Using 3 Ecap Modules
241
ECAP1 Initialization for Multichannel PWM Generation with Phase Control
242
ECAP2 Initialization for Multichannel PWM Generation with Phase Control
242
ECAP3 Initialization for Multichannel PWM Generation with Phase Control
242
Registers
243
Time-Stamp Counter Register (TSCTR)
243
Control and Status Register Set
243
Time-Stamp Counter Register (TSCTR) Field Descriptions
243
Counter Phase Control Register (CTRPHS)
244
Capture 1 Register (CAP1)
244
Counter Phase Control Register (CTRPHS) Field Descriptions
244
Capture 1 Register (CAP1) Field Descriptions
244
Capture 2 Register (CAP2)
245
Capture 3 Register (CAP3)
245
Capture 2 Register (CAP2) Field Descriptions
245
Capture 3 Register (CAP3) Field Descriptions
245
Capture 4 Register (CAP4)
246
ECAP Control Register 1 (ECCTL1)
246
Capture 4 Register (CAP4) Field Descriptions
246
ECAP Control Register 1 (ECCTL1) Field Descriptions
246
ECAP Control Register 2 (ECCTL2)
248
ECAP Control Register 2 (ECCTL2) Field Descriptions
248
ECAP Interrupt Enable Register (ECEINT)
249
ECAP Interrupt Enable Register (ECEINT)
250
ECAP Interrupt Enable Register (ECEINT) Field Descriptions
250
ECAP Interrupt Flag Register (ECFLG)
251
ECAP Interrupt Flag Register (ECFLG) Field Descriptions
251
ECAP Interrupt Clear Register (ECCLR)
252
ECAP Interrupt Clear Register (ECCLR) Field Descriptions
252
ECAP Interrupt Forcing Register (ECFRC)
253
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
253
Revision ID Register (REVID)
254
Revision ID Register (REVID) Field Descriptions
254
Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
255
Introduction
256
Submodule Overview
256
Multiple Epwm Modules
257
Submodules and Signal Connections for an Epwm Module
258
Epwm Submodules and Critical Internal Signal Interconnects
259
Register Mapping
260
Epwm Module Control and Status Registers Grouped by Submodule
260
Architecture
261
Overview
261
Submodule Configuration Parameters
261
Proper Interrupt Initialization Procedure
264
Time-Base (TB) Submodule
265
Time-Base Submodule Block Diagram
265
Time-Base Submodule Signals and Registers
266
Time-Base Submodule Registers
266
Key Time-Base Signals
267
Time-Base Frequency and Period
268
Time-Base Counter Synchronization Scheme
269
Time-Base Up-Count Mode Waveforms
271
Time-Base Down-Count Mode Waveforms
272
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
272
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
273
Counter-Compare (CC) Submodule
274
Counter-Compare Submodule
274
Counter-Compare Submodule Signals and Registers
274
Counter-Compare Submodule Registers
275
Counter-Compare Submodule Key Signals
275
Counter-Compare Event Waveforms in Up-Count Mode
277
Counter-Compare Events in Down-Count Mode
277
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
278
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
278
Action-Qualifier (AQ) Submodule
279
Action-Qualifier Submodule
279
Action-Qualifier Submodule Registers
279
Action-Qualifier Submodule Inputs and Outputs
280
Action-Qualifier Submodule Possible Input Events
280
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
281
Action-Qualifier Event Priority for Up-Down-Count Mode
282
Action-Qualifier Event Priority for Up-Count Mode
282
Action-Qualifier Event Priority for Down-Count Mode
282
Behavior if CMPA/CMPB Is Greater than the Period
283
Up-Down-Count Mode Symmetrical Waveform
284
Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
285
Epwmx Initialization for
286
Epwmx Run Time Changes for
286
Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
287
Epwmx Initialization for
288
Epwmx Run Time Changes for
288
Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
289
Epwmx Initialization for
290
Epwmx Run Time Changes for
290
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
291
Epwmx Initialization for
292
Epwmx Run Time Changes for
292
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary
293
Epwmx Initialization for
294
Epwmx Run Time Changes for
294
Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
295
Epwmx Initialization for
296
Epwmx Run Time Changes for
296
Dead-Band Generator (DB) Submodule
297
Dead-Band Generator Submodule
297
Dead-Band Generator Submodule Registers
297
Configuration Options for the Dead-Band Generator Submodule
298
Classical Dead-Band Operating Modes
299
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
300
PWM-Chopper (PC) Submodule
301
PWM-Chopper Submodule
301
PWM-Chopper Submodule Registers
301
PWM-Chopper Submodule Signals and Registers
302
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
303
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
303
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
304
Trip-Zone (TZ) Submodule
305
Trip-Zone Submodule
305
Trip-Zone Submodule Registers
306
Possible Actions on a Trip Event
307
Trip-Zone Submodule Mode Control Logic
308
Trip-Zone Submodule Interrupt Logic
308
Event-Trigger (ET) Submodule
309
Event-Trigger Submodule
309
Event-Trigger Submodule Registers
309
Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
310
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
310
Event-Trigger Interrupt Generator
312
High-Resolution PWM (HRPWM) Submodule
313
HRPWM System Interface
313
Resolution Calculations for Conventionally Generated PWM
314
Resolution for PWM and HRPWM
314
Operating Logic Using MEP
315
HRPWM Submodule Registers
315
Relationship between MEP Steps, PWM Frequency and Resolution
316
Required PWM Waveform for a Requested Duty
317
CMPA Vs Duty (Left), and [CMPA:CMPAHR] Vs Duty (Right)
317
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
319
High % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
319
Applications to Power Topologies
320
Overview of Multiple Modules
320
Simplified Epwm Module
320
Key Configuration Capabilities
321
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
321
Controlling Multiple Buck Converters with Independent Frequencies
322
Control of Four Buck Stages
322
Pwm1 Pwm2 Pwm3 Pwm4
322
Buck Waveforms for
323
EPWM1 Initialization for
324
EPWM2 Initialization for
324
EPWM3 Initialization for
324
Controlling Multiple Buck Converters with same Frequencies
325
Control of Four Buck Stages
325
Pwm2 Pwm1
326
EPWM1 Initialization for
327
EPWM2 Initialization for
327
Controlling Multiple Half H-Bridge (HHB) Converters
328
EPWM1 Initialization for
330
EPWM2 Initialization for
330
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
331
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
331
EPWM1 Initialization for
333
EPWM2 Initialization for
333
EPWM3 Initialization for
334
Practical Applications Using Phase Control between PWM Modules
335
Configuring Two PWM Modules for Phase Control
335
Controlling a 3-Phase Interleaved DC/DC Converter
336
Timing Waveforms Associated with Phase Control between 2 Modules
336
Control of a 3-Phase Interleaved DC/DC Converter
337
EPWM1 Initialization for
339
EPWM2 Initialization for
339
EPWM3 Initialization for
340
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
341
Pwm2 Pwm1
341
ZVS Full-H Bridge Waveforms
342
EPWM1 Initialization for
343
EPWM2 Initialization for
343
Registers
344
Time-Base Submodule Registers
344
Time-Base Control Register (TBCTL)
344
Submodule Registers
344
Time-Base Control Register (TBCTL) Field Descriptions
345
Time-Base Status Register (TBSTS)
346
Time-Base Status Register (TBSTS) Field Descriptions
346
Time-Base Phase Register (TBPHS)
347
Time-Base Counter Register (TBCNT)
347
Time-Base Phase Register (TBPHS) Field Descriptions
347
Time-Base Counter Register (TBCNT) Field Descriptions
347
Counter-Compare Submodule Registers
348
Time-Base Period Register (TBPRD)
348
Time-Base Period Register (TBPRD) Field Descriptions
348
Counter-Compare Control Register (CMPCTL)
349
Counter-Compare Control Register (CMPCTL) Field Descriptions
349
Counter-Compare a Register (CMPA)
350
Counter-Compare a Register (CMPA) Field Descriptions
350
Action-Qualifier Submodule Registers
351
Counter-Compare B Register (CMPB)
351
Counter-Compare B Register (CMPB) Field Descriptions
351
Action-Qualifier Output a Control Register (AQCTLA)
352
Action-Qualifier Output B Control Register (AQCTLB)
353
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
353
Action-Qualifier Software Force Register (AQSFRC)
354
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
354
Dead-Band Generator Submodule Registers
355
Action-Qualifier Continuous Software Force Register (AQCSFRC)
355
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
355
Dead-Band Generator Control Register (DBCTL)
356
Dead-Band Generator Control Register (DBCTL) Field Descriptions
356
Dead-Band Generator Rising Edge Delay Register (DBRED)
357
Dead-Band Generator Falling Edge Delay Register (DBFED)
357
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
357
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
357
PWM-Chopper Submodule Register
358
PWM-Chopper Control Register (PCCTL)
358
PWM-Chopper Control Register (PCCTL) Bit Descriptions
358
Trip-Zone Submodule Registers
359
Trip-Zone Select Register (TZSEL)
359
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
359
Trip-Zone Control Register (TZCTL)
360
Trip-Zone Enable Interrupt Register (TZEINT)
360
Trip-Zone Control Register (TZCTL) Field Descriptions
360
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
360
Trip-Zone Flag Register (TZFLG)
361
Trip-Zone Flag Register (TZFLG) Field Descriptions
361
Trip-Zone Clear Register (TZCLR)
362
Trip-Zone Force Register (TZFRC)
362
Trip-Zone Clear Register (TZCLR) Field Descriptions
362
Trip-Zone Force Register (TZFRC) Field Descriptions
362
Event-Trigger Submodule Registers
363
Event-Trigger Selection Register (ETSEL)
363
Event-Trigger Selection Register (ETSEL) Field Descriptions
363
Event-Trigger Prescale Register (ETPS)
364
Event-Trigger Prescale Register (ETPS) Field Descriptions
364
Event-Trigger Flag Register (ETFLG)
365
Event-Trigger Clear Register (ETCLR)
365
Event-Trigger Flag Register (ETFLG) Field Descriptions
365
Event-Trigger Clear Register (ETCLR) Field Descriptions
365
High-Resolution PWM Submodule Registers
366
Event-Trigger Force Register (ETFRC)
366
Event-Trigger Force Register (ETFRC) Field Descriptions
366
Time-Base Phase High-Resolution Register (TBPHSHR)
367
Counter-Compare a High-Resolution Register (CMPAHR)
367
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions
367
Counter-Compare a High-Resolution Register (CMPAHR) Field Descriptions
367
HRPWM Configuration Register (HRCNFG)
368
HRPWM Configuration Register (HRCNFG) Field Descriptions
368
Enhanced Quadrature Encoder Pulse (Eqep) Module
369
Introduction
370
Optical Encoder Disk
370
QEP Encoder Output Signal for Forward/Reverse Movement
371
Index Pulse Example
371
Architecture
373
EQEP Inputs
373
Functional Description
373
Functional Block Diagram of the Eqep Peripheral
374
Quadrature Decoder Unit (QDU)
375
Functional Block Diagram of Decoder Unit
375
Quadrature Decoder Truth Table
376
Quadrature Decoder State Machine
377
Quadrature-Clock and Direction Decoding
377
Position Counter and Control Unit (PCCU)
378
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
379
Position Counter Underflow/Overflow (QPOSMAX = 4)
380
Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
382
Strobe Event Latch (QEPCTL[SEL] = 1)
383
Eqep Position-Compare Unit
384
Eqep Position-Compare Event Generation Points
385
Eqep Position-Compare Sync Output Pulse Stretcher
385
Eqep Edge Capture Unit
386
Eqep Edge Capture Unit
387
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
387
Eqep Edge Capture Unit - Timing Details
388
Eqep Watchdog
389
Eqep Watchdog Timer
389
Unit Timer Base
390
Eqep Interrupt Structure
390
Eqep Unit Time Base
390
EQEP Interrupt Generation
390
Eqep Registers
391
Eqep Position Counter Register (QPOSCNT)
392
Eqep Position Counter Initialization Register (QPOSINIT)
392
Eqep Maximum Position Count Register (QPOSMAX)
392
Eqep Position Counter Register (QPOSCNT) Field Descriptions
392
Eqep Position Counter Initialization Register (QPOSINIT) Field Descriptions
392
Eqep Maximum Position Count Register (QPOSMAX) Field Descriptions
392
Eqep Position-Compare Register (QPOSCMP)
393
Eqep Index Position Latch Register (QPOSILAT)
393
Eqep Strobe Position Latch Register (QPOSSLAT)
393
Eqep Position-Compare Register (QPOSCMP) Field Descriptions
393
Eqep Index Position Latch Register (QPOSILAT) Field Descriptions
393
Eqep Strobe Position Latch Register (QPOSSLAT) Field Descriptions
393
Eqep Position Counter Latch Register (QPOSLAT)
394
Eqep Unit Timer Register (QUTMR)
394
Eqep Unit Period Register (QUPRD)
394
Eqep Position Counter Latch Register (QPOSLAT) Field Descriptions
394
Eqep Unit Timer Register (QUTMR) Field Descriptions
394
Eqep Unit Period Register (QUPRD) Field Descriptions
394
Eqep Watchdog Timer Register (QWDTMR)
395
Eqep Watchdog Period Register (QWDPRD)
395
Eqep Watchdog Timer Register (QWDTMR) Field Descriptions
395
Eqep Watchdog Period Register (QWDPRD) Field Description
395
QEP Decoder Control Register (QDECCTL)
396
Eqep Decoder Control Register (QDECCTL) Field Descriptions
396
Eqep Control Register (QEPCTL)
397
Eqep Control Register (QEPCTL) Field Descriptions
397
Eqep Capture Control Register (QCAPCTL)
399
Eqep Capture Control Register (QCAPCTL) Field Descriptions
399
Eqep Position-Compare Control Register (QPOSCTL)
400
Eqep Position-Compare Control Register (QPOSCTL) Field Descriptions
400
Eqep Interrupt Enable Register (QEINT)
401
Eqep Interrupt Enable Register (QEINT) Field Descriptions
401
Eqep Interrupt Flag Register (QFLG)
402
Eqep Interrupt Flag Register (QFLG) Field Descriptions
402
Eqep Interrupt Clear Register (QCLR)
403
Eqep Interrupt Clear Register (QCLR) Field Descriptions
403
Eqep Interrupt Force Register (QFRC)
405
Eqep Interrupt Force Register (QFRC) Field Descriptions
405
Eqep Status Register (QEPSTS)
406
Eqep Status Register (QEPSTS) Field Descriptions
406
Eqep Capture Timer Register (QCTMR)
407
Eqep Capture Period Register (QCPRD)
407
Eqep Capture Timer Latch Register (QCTMRLAT)
407
Eqep Capture Time Register (QCTMR) Field Descriptions
407
Eqep Capture Period Register (QCPRD) Field Descriptions
407
Eqep Capture Timer Latch Register (QCTMRLAT) Field Descriptions
407
Eqep Capture Period Latch Register (QCPRDLAT)
408
Eqep Revision ID Register (REVID)
408
Eqep Capture Period Latch Register (QCPRDLAT) Field Descriptions
408
Eqep Revision ID Register (REVID) Field Descriptions
408
Enhanced Direct Memory Access (EDMA3) Controller
409
Introduction
410
Overview
410
Features
410
Functional Block Diagram
412
Terminology Used in this Document
412
EDMA3 Controller Block Diagram
412
Architecture
414
Functional Overview
414
EDMA3 Channel Controller (EDMA3CC) Block Diagram
415
EDMA3 Transfer Controller (EDMA3TC) Block Diagram
416
Types of EDMA3 Transfers
417
Definition of ACNT, BCNT, and CCNT
417
A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
418
AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
419
Parameter RAM (Param)
420
Param Set
420
EDMA3 Channel Parameter Description
421
Dummy and Null Transfer Request
424
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)
425
Linked Transfer Example
428
Link-To-Self Transfer Example
429
Initiating a DMA Transfer
430
Completion of a DMA Transfer
433
Expected Number of Transfers for Non-Null Transfer
433
Event, Channel, and Param Mapping
434
EDMA3 DMA Channel to Param Mapping
435
QDMA Channel to Param Mapping
436
EDMA3 Channel Controller Regions
437
Shadow Region Registers
437
Shadow Region Registers
438
Chaining EDMA3 Channels
439
EDMA3 Interrupts
439
Chain Event Triggers
439
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
440
Number of Interrupts
441
Interrupt Diagram
442
Error Interrupt Operation
445
Event Queue(S)
446
EDMA3 Transfer Controller (EDMA3TC)
448
Event Dataflow
451
EDMA3 Prioritization
452
EDMA3CC and EDMA3TC Performance and System Considerations
454
Read/Write Command Optimization Rules
454
EDMA3 Operating Frequency (Clock Control)
455
Reset Considerations
455
Power Management
455
Emulation Considerations
456
Transfer Examples
456
Block Move Example
456
Block Move Example Param Configuration
457
Subframe Extraction Example
458
Subframe Extraction Example Param Configuration
458
Data Sorting Example
459
Data Sorting Example Param Configuration
460
Peripheral Servicing Example
461
Servicing Incoming Mcbsp Data Example
461
Servicing Incoming Mcbsp Data Example Param
462
Servicing Peripheral Burst Example
463
Servicing Peripheral Burst Example Param
463
Servicing Continuous Mcbsp Data Example
464
Servicing Continuous Mcbsp Data Example Param
465
Servicing Continuous Mcbsp Data Example Reload Param
466
Ping-Pong Buffering for Mcbsp Data Example
468
Ping-Pong Buffering for Mcbsp Example Param
469
Ping-Pong Buffering for Mcbsp Example Pong Param
470
Ping-Pong Buffering for Mcbsp Example Ping Param
470
Intermediate Transfer Completion Chaining Example
472
Single Large Block Transfer Example
472
Registers
473
Parameter RAM (Param) Entries
473
Smaller Packet Data Transfers Example
473
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (Param) Entries
473
Channel Options Parameter (OPT)
474
Channel Options Parameters (OPT) Field Descriptions
474
Channel Source Address Parameter (SRC)
476
A Count/B Count Parameter (A_B_CNT)
476
Channel Source Address Parameter (SRC) Field Descriptions
476
Channel Destination Address Parameter (DST)
477
Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
477
Channel Destination Address Parameter (DST) Field Descriptions
477
Link Address/B Count Reload Parameter (LINK_BCNTRLD)
478
Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
479
C Count Parameter (CCNT)
479
C Count Parameter (CCNT) Field Descriptions
479
EDMA3 Channel Controller (EDMA3CC) Registers
480
Revision ID Register (REVID)
483
EDMA3CC Configuration Register (CCCFG)
483
Revision ID Register (REVID) Field Descriptions
483
EDMA3CC Configuration Register (CCCFG) Field Descriptions
484
QDMA Channel N Mapping Register (Qchmapn)
485
QDMA Channel N Mapping Register (Qchmapn) Field Descriptions
485
DMA Channel Queue Number Register N (Dmaqnumn)
486
DMA Channel Queue Number Register N (Dmaqnumn) Field Descriptions
486
Bits in Dmaqnumn
486
QDMA Channel Queue Number Register (QDMAQNUM)
487
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
487
Event Missed Register (EMR)
488
Event Missed Clear Register (EMCR)
489
QDMA Event Missed Register (QEMR)
490
QDMA Event Missed Register (QEMR) Field Descriptions
490
QDMA Event Missed Clear Register (QEMCR)
491
QDMA Event Missed Clear Register (QEMCR) Field Descriptions
491
EDMA3CC Error Register (CCERR)
492
EDMA3CC Error Register (CCERR) Field Descriptions
492
EDMA3CC Error Clear Register (CCERRCLR)
493
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
493
Error Evaluate Register (EEVAL)
494
Error Evaluate Register (EEVAL) Field Descriptions
494
DMA Region Access Enable Register for Region M (Draem)
495
DMA Region Access Enable Register for Region M (Draem) Field Descriptions
495
QDMA Region Access Enable for Region M (Qraem)
496
QDMA Region Access Enable for Region M (Qraem) Field Descriptions
496
Event Queue Entry Registers (Qxey)
497
Event Queue Entry Registers (Qxey) Field Descriptions
497
Queue N Status Register (Qstatn)
498
Queue N Status Register (Qstatn) Field Descriptions
498
Queue Watermark Threshold a Register (QWMTHRA)
499
Queue Watermark Threshold a Register (QWMTHRA) Field Descriptions
499
EDMA3CC Status Register (CCSTAT)
500
EDMA3CC Status Register (CCSTAT) Field Descriptions
500
Event Register (ER)
502
Event Register (ER) Field Descriptions
502
Event Clear Register (ECR)
503
Event Clear Register (ECR) Field Descriptions
503
Event Set Register (ESR)
504
Chained Event Register (CER)
505
Event Enable Register (EER)
506
Event Enable Clear Register (EECR)
507
Event Enable Set Register (EESR)
507
Secondary Event Register (SER)
508
Secondary Event Clear Register (SECR)
508
Secondary Event Register (SER) Field Descriptions
508
Secondary Event Clear Register (SECR) Field Descriptions
508
Interrupt Enable Register (IER) Field Descriptions
509
Interrupt Enable Clear Register (IECR)
510
Interrupt Enable Set Register (IESR)
510
Interrupt Pending Register (IPR)
511
Interrupt Clear Register (ICR)
512
Interrupt Evaluate Register (IEVAL)
513
Interrupt Evaluate Register (IEVAL) Field Descriptions
513
QDMA Event Register (QER)
514
QDMA Event Register (QER) Field Descriptions
514
QDMA Event Enable Register (QEER)
515
QDMA Event Enable Register (QEER) Field Descriptions
515
QDMA Event Enable Clear Register (QEECR)
516
QDMA Event Enable Set Register (QEESR)
516
QDMA Event Enable Clear Register (QEECR) Field Descriptions
516
QDMA Event Enable Set Register (QEESR) Field Descriptions
516
QDMA Secondary Event Register (QSER)
517
QDMA Secondary Event Register (QSER) Field Descriptions
517
QDMA Secondary Event Clear Register (QSECR)
518
QDMA Secondary Event Clear Register (QSECR) Field Descriptions
518
EDMA3 Transfer Controller (EDMA3TC) Registers
519
Revision ID Register (REVID)
520
Revision ID Register (REVID) Field Descriptions
520
EDMA3TC Configuration Register (TCCFG)
521
EDMA3TC Configuration Register (TCCFG) Field Descriptions
521
EDMA3TC Channel Status Register (TCSTAT)
522
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
522
Error Status Register (ERRSTAT)
523
Error Status Register (ERRSTAT) Field Descriptions
523
Error Enable Register (ERREN)
524
Error Enable Register (ERREN) Field Descriptions
524
Error Clear Register (ERRCLR)
525
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Texas Instruments TMS320C6743 User Manual (35 pages)
Processor Universal Serial Bus (USB1.1) OHCI Host Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
6
Read this First
6
Introduction
8
Purpose of the Peripheral
8
Universal Serial Bus OHCI Host Controller
8
Architecture
9
Clock and Reset
9
Open Host Controller Interface Functionality
10
Differences from OHCI Specification for USB
10
Implementation of OHCI Specification for USB1.1
11
OHCI Interrupts
12
USB1.1 Host Controller Access to System Memory
12
Physical Addressing
12
Relationships between Virtual Address Physical Address
12
Registers
13
USB1.1 Host Controller Registers
13
OHCI Revision Number Register (HCREVISION)
14
HC Operating Mode Register (HCCONTROL)
14
OHCI Revision Number Register (HCREVISION) Field Descriptions
14
HC Operating Mode Register (HCCONTROL) Field Descriptions
15
HC Command and Status Register (HCCOMMANDSTATUS)
16
HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions
16
HC Interrupt and Status Register (HCINTERRUPTSTATUS)
17
HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions
17
HC Interrupt Enable Register (HCINTERRUPTENABLE)
18
HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions
18
HC Interrupt Disable Register (HCINTERRUPTDISABLE)
19
HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions
19
HC HCAA Address Register (HCHCCA)
20
HC Current Periodic Register (HCPERIODCURRENTED)
20
HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions
20
HC Head Control Register (HCCONTROLHEADED)
21
HC HCAA Address Register (HCHCCA) Field Descriptions
20
HC Head Control Register (HCCONTROLHEADED) Field Descriptions
21
HC Current Control Register (HCCONTROLCURRENTED)
22
HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions
22
HC Head Bulk Register (HCBULKHEADED)
23
HC Current Bulk Register (HCBULKCURRENTED)
23
HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions
23
HC Head Done Register (HCDONEHEAD)
24
HC Frame Interval Register (HCFMINTERVAL)
24
HC Head Bulk Register (HCBULKHEADED) Field Descriptions
23
HC Frame Interval Register (HCFMINTERVAL) Field Descriptions
24
HC Frame Remaining Register (HCFMREMAINING)
25
HC Frame Number Register (HCFMNUMBER)
25
HC Head Done Register (HCDONEHEAD) Field Descriptions
24
HC Frame Number Register (HCFMNUMBER) Field Descriptions
25
HC Periodic Start Register (HCPERIODICSTART)
26
HC Frame Remaining Register (HCFMREMAINING) Field Descriptions
25
HC Periodic Start Register (HCPERIODICSTART) Field Descriptions
26
HC Low-Speed Threshold Register (HCLSTHRESHOLD)
27
HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions
27
HC Root Hub a Register (HCRHDESCRIPTORA)
28
HC Root Hub a Register (HCRHDESCRIPTORA) Field Descriptions
28
HC Root Hub B Register (HCRHDESCRIPTORB)
29
HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions
29
HC Root Hub Status Register (HCRHSTATUS)
30
HC Root Hub Status Register (HCRHSTATUS) Field Descriptions
30
HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
31
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions
31
HC Port 2 Status and Control Register (HCRHPORTSTATUS2)
33
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions
33
Important Notice
35
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