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TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
6.7
Interrupts
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
6.7.1 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in
controller controls the generation of the CPU exceptions, NMI, and emulation interrupts.
summarizes the C674x interrupt controller registers and memory locations.
Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU
and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.
EVT#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
92
Peripheral Information and Electrical Specifications
Table 6-6. C6748 DSP Interrupts
Interrupt Name
EVT0
EVT1
EVT2
EVT3
T64P0_TINT12
SYSCFG_CHIPINT2
PRU_EVTOUT0
EHRPWM0
EDMA3_0_CC0_INT1
EMU_DTDMA
EHRPWM0TZ
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
IDMAINT1
MMCSD0_INT0
MMCSD0_INT1
PRU_EVTOUT1
EHRPWM1
USB0_INT
USB1_HCINT
USB1_RWAKEUP
PRU_EVTOUT2
EHRPWM1TZ
SATA_INT
T64P2_TINTALL
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
UHPI_DSPINT
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Table
Source
C674x Int Ctl 0
C674x Int Ctl 1
C674x Int Ctl 2
C674x Int Ctl 3
Timer64P0 - TINT12
SYSCFG CHIPSIG Register
PRUSS Interrupt
HiResTimer/PWM0 Interrupt
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer
Completion Interrupt
C674x-ECM
HiResTimer/PWM0 Trip Zone Interrupt
C674x-RTDX
C674x-RTDX
C674x-EMC
C674x-EMC
MMCSD0 MMC/SD Interrupt
MMCSD0 SDIO Interrupt
PRUSS Interrupt
HiResTimer/PWM1 Interrupt
USB0 Interrupt
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
PRUSS Interrupt
HiResTimer/PWM1 Trip Zone Interrupt
SATA Controller
Timer64P2 Combined TINT12 and TINT 34 Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
UHPI DSP Interrupt
Copyright © 2009–2017, Texas Instruments Incorporated
TMS320C6748
www.ti.com
6-6. Also, the interrupt
Table 6-7
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