Texas Instruments TMS320C6748 Manual page 260

TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
Category Hardware Feature
Watch point
Watch point with Data
Analysis
Counters/timers
External Event Trigger In
External Event Trigger Out
6.34.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
PIN TYPE
TRST I Test Logic Reset
TCK I
TMS I Test Mode Select
TDI I Test Data Input
TDO O Test Data Output
EMU0 I/O Emulation 0
EMU1 I/O Emulation 1
6.34.2 Scan Chain Configuration Parameters
Table 6-144 shows the TAP configuration details required to configure the router/emulator for this device.
Router Port ID Default TAP
17 No
19 No
The router is revision C and has a 6-bit IR length.
6.34.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
6.34.4 IEEE 1149.1 JTAG
(1)
The JTAG interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
260 Peripheral Information and Electrical Specifications
Table 6-142. DSP Debug Features (continued)
Up to 4 watch points, which are shared with HWBPs, and can also be used as 2 watch
Table 6-143. JTAG Port Description
NAME
When asserted (active low) causes all test and debug logic in the device to be reset
along with the IEEE 1149.1 interface
Test Clock This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
Scan data output of the device
Channel 0 trigger + HSRTDX
Channel 1 trigger + HSRTDX
Table 6-144. JTAG Port Description
TAP Name
C674x
ETB
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Availability
points with data (32 bits)
Up to 2, Which can also be used as 4 watch points.
1x64-bits (cycle only) + 2x32-bits (water mark counters)
1
1
DESCRIPTION
Tap IR Length
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TMS320C6748
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