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6.11 DDR2/mDDR Memory Controller
The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports
JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
The DDR2/mDDR Memory Controller support the following features:
•
JESD79-2A standard compliant DDR2 SDRAM
•
Mobile DDR SDRAM
•
256 MByte memory space for DDR2
•
256 MByte memory space for mDDR
•
CAS latencies:
– DDR2: 2, 3, 4 and 5
– mDDR: 2 and 3
•
Internal banks:
– DDR2: 1, 2, 4 and 8
– mDDR:1, 2 and 4
•
Burst length: 8
•
Burst type: sequential
•
1 chip select (CS) signal
•
Page sizes: 256, 512, 1024, and 2048
•
SDRAM autoinitialization
•
Self-refresh mode
•
Partial array self-refresh (for mDDR)
•
Power down mode
•
Prioritized refresh
•
Programmable refresh rate and backlog counter
•
Programmable timing parameters
•
Little endian
6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
Table 6-23. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR
No.
Cycle time,
1
t
c(DDR_CLK)
DDR_CLKP / DDR_CLKN
(1) DDR2 is not supported at this voltage operating point.
Copyright © 2009–2017, Texas Instruments Incorporated
Memory Controller
PARAMETER
DDR2
mDDR
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Product Folder Links:
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
1.3V, 1.2V
1.1V
MIN
MAX
MIN
MAX
125
156
125
150
105
150
100
133
Peripheral Information and Electrical Specifications
TMS320C6748
TMS320C6748
1.0V
UNIT
MIN
MAX
(1)
(1)
—
—
MHz
95
133
119
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