Table of Contents
Advertisement
www.ti.com
6.34 Emulation Logic
The debug capabilities and features for DSP are as shown below.
DSP:
•
Basic Debug
– Execution Control
– System Visibility
•
Real-Time Debug
– Interrupts serviced while halted
– Low/non-intrusive system visibility while running
•
Advanced Debug
– Global Start
– Global Stop
– Specify targeted memory level(s) during memory accesses
– HSRTDX (High Speed Real Time Data eXchange)
•
Advanced System Control
– Subsystem reset via debug
– Peripheral notification of debug events
– Cache-coherent debug accesses
•
Analysis Actions
– Stop program execution
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
•
Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
•
Analysis Configuration
– Application access
– Debugger access
Category
Hardware Feature
Software breakpoint
Basic Debug
Hardware breakpoint
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
Copyright © 2009–2017, Texas Instruments Incorporated
Table 6-142. DSP Debug Features
(1)
4 precise
HWBPs inside DSP core and one of them is associated with a counter.
(1)
4 imprecise
HWBPs from AET which are shared for watch point.
Submit Documentation Feedback
Product Folder Links:
TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
Availability
Unlimited
Up to 10 HWBPs, including:
(1)
2 imprecise
HWBPs from AET.
Peripheral Information and Electrical Specifications
TMS320C6748
259
Advertisement
Table of Contents
