Functional Block Diagram - Texas Instruments TMS320C6748 Manual

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1.4

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.
Input
Clock(s)
Peripherals
DMA Audio Ports
EDMA3 McASP
(x2) w/FIFO
Customizable Interface
USB2.0
PRU Subsystem
OTG Ctlr
PHY
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JTAG Interface
System Control
PLL/Clock
Generator
Memory
w/OSC
Protection
General-
Purpose
Timer (x3)
Power/Sleep
Controller
RTC/
32-kHz Pin
OSC
Multiplexing
Switched Central Resource (SCR)
Serial Interfaces
2
SPI UART
McBSP I C
(x2) (x3)
(x2) (x2)
Connectivity
EMAC
USB1.1
10/100
OHCI Ctlr MDIO
(MII/RMII)
PHY
Figure 1-1. Functional Block Diagram
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SPRS590G – JUNE 2009 – REVISED JANUARY 2017
DSP Subsystem
C674x™
DSP CPU
AET
32KB
32KB
L1 Pgm
L1 RAM
256KB L2 RAM
BOOT ROM
Display Parallel Port Internal Memory
LCD 128KB
uPP
Ctlr RAM
Video
MMC/SD
(8b)
HPI SATA
VPIF
(x2)
TMS320C6748
TMS320C6748
Control Timers
ePWM eCAP
(x2) (x3)
External Memory Interfaces
EMIFA(8b/16B)
DDR2/MDDR
NAND/Flash
Controller
16b SDRAM
Device Overview 5