Lcd Controller (Lcdc) - Texas Instruments TMS320C6748 Manual

www.ti.com

6.24 LCD Controller (LCDC)

The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
• The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
• The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability
of control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate. For details, see
Table 6-107 lists the LCD Controller registers.
BYTE ADDRESS
0x01E1 3000
0x01E1 3004
0x01E1 3008
0x01E1 300C
0x01E1 3010 LIDD_CS0_CONF
0x01E1 3014 LIDD_CS0_ADDR
0x01E1 3018
0x01E1 301C LIDD_CS1_CONF
0x01E1 3020 LIDD_CS1_ADDR
0x01E1 3024
0x01E1 3028
0x01E1 302C RASTER_TIMING_0
0x01E1 3030 RASTER_TIMING_1
0x01E1 3034 RASTER_TIMING_2
0x01E1 3038 RASTER_SUBPANEL
0x01E1 3040
0x01E1 3044 LCDDMA_FB0_BASE
0x01E1 3048 LCDDMA_FB0_CEILING
0x01E1 304C LCDDMA_FB1_BASE
0x01E1 3050 LCDDMA_FB1_CEILING
Copyright © 2009–2017, Texas Instruments Incorporated
Table 6-107. LCD Controller Registers
ACRONYM
REVID LCD Revision Identification Register
LCD_CTRL LCD Control Register
LCD_STAT LCD Status Register
LIDD_CTRL LCD LIDD Control Register
LCD LIDD CS0 Configuration Register
LCD LIDD CS0 Address Read/Write Register
LIDD_CS0_DATA LCD LIDD CS0 Data Read/Write Register
LCD LIDD CS1 Configuration Register
LCD LIDD CS1 Address Read/Write Register
LIDD_CS1_DATA LCD LIDD CS1 Data Read/Write Register
RASTER_CTRL LCD Raster Control Register
LCD Raster Timing 0 Register
LCD Raster Timing 1 Register
LCD Raster Timing 2 Register
LCD Raster Subpanel Display Register
LCDDMA_CTRL LCD DMA Control Register
LCD DMA Frame Buffer 0 Base Address Register
LCD DMA Frame Buffer 0 Ceiling Address Register
LCD DMA Frame Buffer 1 Base Address Register
LCD DMA Frame Buffer 1 Ceiling Address Register
Submit Documentation Feedback
Product Folder Links:
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
REGISTER DESCRIPTION
Peripheral Information and Electrical Specifications
TMS320C6748
TMS320C6748
SPRAB93.
205