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4 Device Configuration
4.1
Boot Modes
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
See Using the TMS320C6748/C6746/C6742 Bootloader (SPRAAT2) for more details on the ROM Boot
Loader.
The following boot modes are supported:
•
NAND Flash boot
– 8-bit NAND
– 16-bit NAND (supported on ROM revisions after d800k002 -- see the bootloader documents
mentioned above to determine the ROM revision)
•
NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
•
HPI Boot
•
I2C0/I2C1 Boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
•
SPI0/SPI1 Boot
– Serial Flash (Master Mode)
– SERIAL EEPROM (Master Mode)
– External Host (Slave Mode)
•
UART0/UART1/UART2 Boot
– External Host
•
MMC/SD0 Boot
4.2
SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
Readable Device, Die, and Chip Revision ID
•
Control of Pin Multiplexing
•
Priority of bus accesses different bus masters in the system
•
Capture at power on reset the chip BOOT pin values and make them available to software
•
Control of the DeepSleep power management function
•
Enable and selection of the programmable pin pullups and pulldowns
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TMS320C6748
TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
Device Configuration
71
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