Pin Multiplexing Control 26 - Texas Instruments TMS320C6748 Manual

TMS320C6748
SPRS590G – JUNE 2009 – REVISED JANUARY 2017
• Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 transfer controllers
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the McASP
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA
– DDR2 Controller PHY settings
– SATA PHY power management controls
• Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function.
Many registers are accessible only by a host (DSP) when it is operating in its privileged mode. (ex. from
the kernel, but not from user space code).
Table 4-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS
0x01C1 4000
0x01C1 4008
0x01C1 400C
0x01C1 4010
0x01C1 4014
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
72 Device Configuration
ACRONYM
REVID Revision Identification Register
DIEIDR0 Device Identification Register 0
DIEIDR1 Device Identification Register 1
DIEIDR2 Device Identification Register 2
DIEIDR3 Device Identification Register 3
BOOTCFG Boot Configuration Register
KICK0R Kick 0 Register
KICK1R Kick 1 Register
HOST1CFG Host 1 Configuration Register
IRAWSTAT Interrupt Raw Status/Set Register
IENSTAT Interrupt Enable Status/Clear Register
IENSET Interrupt Enable Register
IENCLR Interrupt Enable Clear Register
EOI End of Interrupt Register
FLTADDRR Fault Address Register
FLTSTAT Fault Status Register
MSTPRI0 Master Priority 0 Registers
MSTPRI1 Master Priority 1 Registers
MSTPRI2 Master Priority 2 Registers
PINMUX0 Pin Multiplexing Control 0 Register
PINMUX1 Pin Multiplexing Control 1 Register
PINMUX2 Pin Multiplexing Control 2 Register
PINMUX3 Pin Multiplexing Control 3 Register
PINMUX4 Pin Multiplexing Control 4 Register
PINMUX5 Pin Multiplexing Control 5 Register
PINMUX6 Pin Multiplexing Control 6 Register
PINMUX7 Pin Multiplexing Control 7 Register
PINMUX8 Pin Multiplexing Control 8 Register
PINMUX9 Pin Multiplexing Control 9 Register
PINMUX10 Pin Multiplexing Control 10 Register
PINMUX11 Pin Multiplexing Control 11 Register
PINMUX12 Pin Multiplexing Control 12 Register
PINMUX13 Pin Multiplexing Control 13 Register
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REGISTER ACCESS
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