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3.1
Write Grayscale Data Into Memory
3.1.1 Memory Structure Overview
To get a high visual display refresh rate and high contrast in an LED display, the data transfer rate is
biggest barrier for traditional LED driver devices. To break this barrier, the TLC694x device implements a
display memory unit. With this memory, a single TLC6946 device can support a maximum of 32 scan
lines, which means maximum 32-multiplexing in each LED display system; and a single TLC6948 device
can support a maximum of 48 scan lines, which means maximum 48-multiplexing in each LED display
system.
The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the normal
operation, one BANK is selected for the current-frame image display, and the other BANK is used to write
the next-frame image data. The BANK selection is determined by the BANK_SEL bit, which is an internal
flag register bit.
After power on, BANK_SEL is initialized to 0, and BANK A is selected to be written into the next frame
image data with the serial-data shift-in clock (SCLK). Meanwhile, the data in BANK B is read out for the
current frame image display with the PWM grayscale control clock (GCLK). When the time of one frame
has elapsed, the external controller sends the vertical synchronization (VSYNC) command. Then the
BANK_SEL bit value is toggled and the selection of the two BANKs reverses. Repeat this operation until
all the frame images are displayed.
With this method, the TLC694x device can display the current frame image at a very high refresh rate,
without any data-transfer-rate barrier. See
operation.
26
PWM Grayscale Control
TI Information — Selective Disclosure
Figure 3-1
for more details about the BANK-selection exchange
Copyright © 2018–2019, Texas Instruments Incorporated
SLVUBF4A – February 2018 – Revised June 2019
PWM Grayscale Control
SLVUBF4A – February 2018 – Revised June 2019
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Chapter 3
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