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10-16
Status Structure
Event registers
As
Figure 10-1
the appropriate event register bit sets to 1. The bit remains latched to 1 until the register is
reset. Reading an event register clears the bits of that register. *CLS resets all four event
registers.
The commands to read the event registers are listed in
registers, see
Table 10-5
Common and SCPI commands — event registers
*ESR?
STATus
:OPERation:[:EVENt]?
:MEASurement:[:EVENt]?
:QUEStionable:[:EVENt]?
Note: Power-up and *CLS resets all bits of all event registers to 0. STATus:PRESet has no effect.
Event enable registers
As
Figure 10-1
bit is logically ANDed (&) to a corresponding enable bit of an enable register. Therefore,
when an event bit is set and the corresponding enable bit is set (as programmed by the
user), the output (summary) of the register will set to 1, which in turn sets the summary bit
of the status byte register.
The commands to program and read the event enable registers are listed in
details on programming and reading registers, see
page 10-5
klqb
shows, each status register set has an event register. When an event occurs,
"Reading registers," page
Command
shows, each status register set has an enable register. Each event register
and
"Reading registers," page
The bits of any enable register can be reset to 0 by sending the
0 parameter value with the appropriate enable command
(i.e. STATus:OPERation:ENABle 0).
Table
10-6.
Description
Read standard event status register.
STATus subsystem:
Read operation event register.
Read measurement event register.
Read questionable event register.
"Programming enable registers,"
10-6.
Model 6487 Reference Manual
10-5. For details on reading
Table
10-6. For
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