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REV.-A
2.2.4 Summary of the Control Circuit
Figure 2-4 shows the block diagram for the control circuit. The control circuit
is comprised of the SEIMA board and the SEIPNL board. The SEIMA board drives the mechanisms for
interfacing between the host computer and data and print data
expansion. LSI's are used in most of the logic circuits for CPU load reduction
(which increase data throughput). These data arrays contain the address codes for mode registers and
command execution. After each mode has been set according to the program at initialization, the
operation is controlled by a single easy instruction. The SEIPNL board controls the operation by serial
interfacing with the SEIMA board. The main IC's used in the logic control part of the control circuit are
described below.
CPU:
H064180 (CPU,10C)
The HD64180 is a single chip equipped with a high-speed CPU, a memory management unit (MMU),
a DMA controller, a timer, an asynchronous serial communications interface (ASCI), and a block
synchronous serial I/O command port. The internal program (12B) is executed by the RESET command,
and oscillation is carried out by the oscillator and is driven in 9.216 MHz (18.432/2 MHz). 512 Kbytes
of physical address space can be accessed by the MMU, which controls the memory and gate arrays
described below. Data buses and lower-position address buses are connected between each gate array
and the CPU, and interfacing is carried out according to MMIO (Memory Mapped I/O) address
Read/Write.
Memory:
27512 (PROM, 12B)
The memory is the CPU program ROM which contains the firmware that controls the
mechanisms, handles ESC/P, and controls the interface and all of the control programs for the main
printer.
M40A33CA (4-Mbyte CG: Character Generator, lOB)
A mask ROM which contains multi-font character generation is provided as standard equipment.
HM65256 (256-Kbyte PSRAM, 11 B)
This PSRAM is used as the CPU working area. Internally, it is mapped as the print data expansion area
for the data input buffer, line buffer, image buffer, etc.
043257 (256-Kbyte SRAM, 13C)
This SRAM stores data for SELECTYPE settings, TOF positions, TEAR OFF amount, etc. When power
is off, these data are protected by the lithium batter (BAT 1).
ER59256 (EEPROM, SEIPNL Board)
This EEPROM stores and protects the hardware settings for the bi-directional adjustment value, the TE
holder position adjustment value, PROM ID's for columns 80-136, etc. If the combination of panels and
mechanisms changes, the settings are rewritten by the adjustment cartridge.
2-7
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