Epson SQ-B50/2550 Technical Manual page 129

REV.-A
Current limit control:
The current limit control circuit is shown in Figure 2-71. EA2 of 494 limits current. The reverse terminal
of EA2 supplies voltage that is divided +36VDC by the zenadiode ZD5 for the voltage drop level of
R52. The non-reverse terminal of EA2 is connected to the source current detection resistor R73 of FET
(3D). This limits the current to approximately O.14A.
T1
GH GH
ZD3
R55
R52
Figure 2-72. Current Limit Circuit
Over-voltage limit circuit:
The over-voltage limit circuit is a cut off circuit to protect the piezoelectric element of the head from
damage due to excessive Vh. The voltage setting at +27.6 (27+0.6)VDC by zenadiode ZD3 and VBE
of 024 maintains a voltage drop level of R218 + R21 7 at about 168VDC. Accordingly, if the Vh output
level exceeds 168VDC, the 024 turns off, and the error amplifier feedback terminal FB (3-pin) of 494
(3C) declines to the ground level to cut off Vh.
Vh
~
168VDC
R 218
R 217
. - - - - - FB <3C:3pin)
Q
24
GH
G H G H
Figure 2-73. Over-voltage Limit Circuit
2-61