Epson SQ-B50/2550 Technical Manual page 124

REV.-A
2.4.2.8 Printer Head Controls
A block diagram of the print head control circuit is shown in Figure 2-62. (For the exact location, refer
to the Appendixes for the SEIMA board circuit diagram and 8-13/I-J.)
This circuit is designed for indirect control of data and the entire drive circuit by the print head controller
E05A22EA (PHC:6B) and does not rely on direct control by the CPU. The PHC is enabled by the MMIOO 1
signal from the MMU.
The CPU reads and writes instruction data for MMIO addresses (AO-A3). The PHC functions after
decoding that instruction data.
<
Character data>
Character data is developed as "image data" that is needed to drive the print head and actually form
the pattern of the character. The PIF, in response to DREQ signals, demands direct memory access (DMA)
transmission of image data and reads it from the character generator (CG). Read image data is developed
by the internal selector/register to coincide with the printing direction and nozzle arrangement
(even/odd). Therefore, the CPU has to begin the printing process and the actual printing task is executed
automatically by the direct memory access controller and the DCU.
<
Charge and discharge control>
Developed character data is latched at output ports H 1 to H24. The PHC generates printing pulses
(charge and discharge pulses) separately for odd and even nozzle lines, based upon the PTS signals
generated at the DCU. External crystal CR2 provides a reference pulse for timing and width of charge
and discharge pulse.
Discharge signals are sent to port Hn (n is 1 to 24). A charge pulse is given to port CHA and CHB of
the PHC and works for charge selection of the head drive voltage Vh, for odd or even line nozzles.
DO"""'"D7
Print head
I nternal Selector
/Register
LZ1008AD
(5C/6C/7C)
AO-A3
PTS
(from DC U )
I
RDY
I
I
Decoder
I
CR2
~
I
t
PHC (6B)
+24
CHA CHB
E%
Vh
Vh supply Vh
Odd
Circuit
Vh
SWithing
Ink Temperat ure
Thermi ster
Figure 2-63. Print Head Control Circuit Block Diagram
2-56