Epson SQ-B50/2550 Technical Manual page 139

MMU
(8 8 )
REV.-A
2.4.4 Vx Power Supply Circuit and Reset Signal Circuit
The Vx power supply circuit generates a power on reset signal. See SEIMA board circuit diagram of
the Appendixes, location A-B/11-12.
When operation begins, transistor 01 and 02 come on when the voltage of the +24VDC line reaches
18.8VDC (ZD 1 voltage 18.2 + Q.6V) to induce + 5VDC to the Vx line. At this time, Vx is ground level.
Vx and +5VDC wave forms are shown in Figure 2-85.
The Vx signal is connected to THLD and DISC terminals of the MMU (8B). The reset generator is equipped
with an MMU that generates power-on reset signals for various chips. This is described in the block
diagram of Figure 2-86.
The initialization signal from the host is latched at the 12-pin PIF (12C) from where it goes to the INT2
terminal of the CPU (1 QC) where the interrupt software is reset. (For more details about the circuit, see
the SEIMA board circuit diagram, location 4/E).
,
~
""
,
Dol
5V
~
V
0·55
Upper: Vx line
Lower: + 5VDC
Figure 2-86. Vx Power Supply Wave Form
V
x
V
x
I
11...-_-1
THLD
L . . . . . - - - - i
DI SC ROUT
1 - - - - (
RS T)--...---
Ext.
CG Board
.....--Option
I/F
"'--PIF(12C)
.--MCU(2A)
...--CPU(10C)
. . . - - PHC
(68)
...--DCU(48)
Figure 2-87. Block Diagram of Power-On Reset Pulse Supply
2-71