Epson SQ-B50/2550 Technical Manual page 140

REV.-A
2.4.5 Timer and Backup Circuitry
The timer and backup circuit are shown in Figure 2-87. (For more details about the circuit, refer to the
SEIMA board circuit diagram of the Appendix, location 8-10/G-H).
The timer circuit provides the timing needed for pump unit operation to the CPU, regardless of the power
status (ON/OFF). The timer circuit consists of a clock and a counter. Both CTSO and RTSO signals form
a serial interface with the CPU.
The CTSO signal is a timer check signal. The counter 292 (130) of the timer circuit makes the signal
go LOW when the preset time value (approximately 145.6 hours) is up. The RTSO signal is a timer reset
signal. When the RTSO signal is LOW, the CLR terminal of counter 292 in the timer circuit goes to ground
level to reset the timer.
The backup circuit backs up SRAM (43257: 13C) and the timer circuit while the power supply is off.
SRAM stores the panel settings and is maintained even when power is off. The circuit also monitors
+5VOC.
When power is supplied, + 5VOC is provided to the Vbak line. If the voltage of the + 5VOC line drops
down to + 4.6VOC (Z02 voltage 4.0V + 022 VBEO.6V). + 3.6VOC ofthe lithium battery BAT 1 is supplied
to the Vbak line. The operation status of the backup circuit when power is off is shown in Figure 2-88.
The timer circuit works with +5VOC while the power supply is turned on and works with Vbak voltage
if the power supply is off. Figure 2-89 shows a wave form of the clock circuit while the power supply
is off. The figure clearly shows that working voltage is switched from + 5VOC to + 3.6VOC.
Voo of 43257(SRAM :13C)
~
-111~
V bak
Ti mer C ircui t
Circuit
-------r------
I CTSO
CPU
(Vbak)
Clock
I
(10 C)
I
Counter
RTSO
(6257: 13 E) :( 292 : 1 30)
~D~
CR4 (32.768KHz)
Figure 2-88. Timer and Backup Circuit Block Diagram
2-72