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REV.-A
CPU Timing
• Two oscillator cycles define one state.
• One machine cycle, such as OP (operational) code fetch or memory read/write, requires three states.
a) OP code fetch timing
During the first half of state
n,
the contents of the program counter (PC) are output on address bus
lines AO to A 18. During the latter half of state
n,
the
ME
and RD signals go active, and the memory
is accessed.
The OP codes on the data busses are fetched at the trailing clock of state T2.
The L1R signal goes active from the first half of state
n
to that of state T3, and indicates that this cycle
is an OP code fetch cycle.
I"
OP code fetch cycle
"I
T1
T2
T3
Tl
T2
Ao -
Al8
Do -
07
==x
!
PC
!
X
PC+ 1
I
I
I
,..1_ _---...,
- - - - - -..... : --«
OP code
)>-------
1
I
--------~---------------
- - - - - - - -
I
- - - - - - - - - - - - - - -
~
!
1
I
\ :
1
\.....__
I
\ :
1
\
I
1....-._-
Figure A-3. OP Code Fetch Timing
b) Memory Data Read/Write Timing
The memory data access timing is different from the OP code fetch timing in the following points:
• The L1R signal does not go active.
• Read data is valid a half clock later, as comparing with the OP code fetch timing. (The data is fetched
at the trailing clock of state T3.)
For memory data write timing, the
ME
signal and WR signal are activated at the latter half of state
n
and the first half of state T2, respectively, and the write data is output on DO to D7 from the latter half
of state
n.
The
ME
and WR signals go inactive in the latter half of state T3, and the write data remains
valid on the data bus unitl just before state T1 starts.
1· ..__
R_ea_d_c_ir_c_le_ _• ..
I... •__
w_r_it_e_c_ir..;..c1..;..e_ _ ..
1 ....__
Tl
12
1'3
Tl
12
1'3
Tl
AO- A18
DO- D7
==x
Memory ;address:
X
;Memor
y :
address
x==
I
I
I
I
------l!-«Read
?ato/--t-<~w:':"r-;'i;l:-te-d:-a~ta----">--
_______
~
__
~---L--~--------
------./ : \...-t---+-- / : '-------_.
\ : :1 :\ :
I
'--
I
I
I
I
\
I
I1
I
I
' - -
I
I
I
I
I
I
I
I
I
I
I
\
I
1
I
I
I
I
Figure A·4. Memory Data Read/Write Timing
A-5
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