Periphbitgrpset - Set Bit Group To Given Value - Freescale Semiconductor DSP56800E User Manual

Core System Infrastructure
Caution: This macro is the optimal way how to set the specified group of bits to given value.
However, it must be kept in mind that during the short time between these two bit operations, the
target memory location goes through the third state where the bit group contains zeroes.
Example 2-25. periphBitGrpZS macro usage
periphBitGrpZS(0x007f, 10, &ArchIO.Pll.plldb);
This code sets the lower 7 bits of PLL Divide-By register to the value 10. Other bits in the register
are not affected.
2.4.2.9

periphBitGrpSet - set bit group to given value

Call(s):
void periphBitGrpSet(UWord16 GroupMask, UWord16 Mask,
Arguments:
GroupMask
Mask
pAddr
Description: The periphBitGrpSet macro sets the bit group to a given value in a memory location
addressed by parameter pAddr. All bits specified by GroupMask are affected. The bits are either
set if the corresponding bits in Mask value are also set or they are cleared if the corresponding bits
in Mask value are cleared.
This variant uses the accumulator and read-modify-write instructions to accomplish the requested
operation. The memory location is first read to accumulator, the bfclr and bfset instructions are
performed on accumulator and the result value is then written back to memory location.
Caution: It might seem this macro is the "proper" way how to set the group of bits to certain
value as there are no intermediate invalid values written in the target memory location. However,
it is quite dangerous to use this macro when interrupts may occur between the read and write
operations. If the interrupt service routine would write the other portion of the target memory
location, the written value could be overwritten back with its previous state by the write
accumulator operation of periphBitGrpSet.
Example 2-26. periphBitGrpSet macro usage
periphBitGrpSet(0x007f, 10, &ArchIO.Pll.plldb);
This code sets the lower 7 bits of PLL Divide-By register to the value 10. Other bits in the register
are not affected (but see "Caution" above).
2-18
UWord16 *pAddr);
Table 2-11. periphBitSet arguments
in Group mask
in "ones" bit mask.
in The memory address.
Targeting 56F8xxx Platform FREESCALE SEMICONDUCTOR