Flexcan Message Identifiers - Freescale Semiconductor DSP56800E User Manual

PROP_SEG = FCCTL0.PROPSEG + 1 [tq]
PHASE_SEG1, PHASE_SEG2 - Phase Buffer Segments
These Phase Buffer Segments are used to compensate the edge phase errors. These segments can
be lengthened or shortened by re-synchronization (SJW parameter). The length of Phase Buffer
Segments can be configured in PSEG1 and PSEG2 fields of the FCCTL1 register.
PHASE_SEG1 = FCCTL1.PSEG1 + 1 [tq]
PHASE_SEG2 = FCCTL1.PSEG2 + 1 [tq]
RE-SYNCHRONIZATION JUMP WIDTH (RJW)
As a result of re-synchronization, PHASE_SEG1 may be lengthened or PHASE_SEG2 may be
shortened. The amount of lengthening or shortening of the Phase Buffer Segments has an upper
bound given by the Re-synchronization Jump Width. This parameter can be configured in RJW
field of the FCCTL1 register.
RJW = FCCTL1.RJW + 1 [tq]
For more information about bit timing requirements, see the CAN 2AB standard document or
Motorola Application Note number 1798 (order number AN1798/D).
5.7.2.2

FlexCAN Message Identifiers

CAN Standard 2.0 defines two kinds of CAN message identifiers. Part A of the standard defines
"standard" 11 bit message identifier and part B defines "extended" 29 bit identifier. The CAN
message header contains control bit named "ID Extended" (IDE) which, when set, identifies
message with 29 bit extended identifier. In Part A-message format the IDE bit is reserved for
future use ("r1") and has always a value of zero.
The Remote Transmit Request (RTR) bit, which follows the 11 bit identifier in standard ID
messages is replaced with "dummy" Substitute Remote Request (SRR) bit in extended 29 bit ID
messages. The SRR is always transmitted as one. For extended ID messages, 18 ID bits added and
a new RTR bit are appended after IDE bit.
FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 5-237