Quick Reference - Freescale Semiconductor DSP56800E User Manual

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Quick Reference

This section defines the terms and formulas used later in Section 5.7.3.

Module base address

FlexCAN (CAN_BASE)

FlexCAN2 (CAN2_BASE)

FlexCAN Bit-Timing

The FlexCAN module supports a variety of means to setup the bit timing required by the CAN

protocol. The main FlexCAN clock is called serial clock or sclock. The ratio between system

clock and sclock can be specified using the PRES_DIV prescaler value in the FCCTL1 register.

sclock = system clock / (FCCTL1.PRES_DIV+1)

A single sclock cycle defines a basic time unit called "time quantum" (tq). All other FlexCAN

timing parameters are measured in the time quanta units.

1/sclock = 1 time quantum

The nominal bit rate of the CAN bus is based on the nominal bit time interval.

nominal bit rate = 1 / nominal bit time

The nominal bit time is split to four non-overlapping time intervals, each measured in time quanta

SYNC_SEG - Synchronization Segment

This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected

to lie within this segment. This part is always 1 tq long.

SYNC_SEG = 1 [tq]

PROP_SEG - Propagation Segment

This part of the bit time is used to compensate for the physical delay times within the network. It

is twice the sum of the signal's propagation time on the bus line, the input comparator delay, and

the output driver delay. The PROPSEG field of the FCCTL0 contains the length of the

PROP_SEG part in tq units

Table 5-177. FlexCAN Module Base Address

nominal bit time

Targeting 56F8xxx Platform

MC56F802x/3x

bit sample point

FREESCALE SEMICONDUCTOR

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