Intc Driver; Introduction; Quick Reference; Api Definition - Freescale Semiconductor DSP56800E User Manual

5.2

INTC Driver

This section describes the API for the MC56F83xx and MC56F80xx Interrupt Controller (INTC)
on-chip module. The functionality of the INTC module itself is described in the Data Sheets of
each particular device.
5.2.1

Introduction

The MC56F83xx/MC56F80xx interrupt system consists of the Interrupt unit in the processor core
and of the Interrupt Controller Module (INTC). The processor core supports four interrupt priority
levels with hardware support for interrupt nesting. Priority levels 0-2 are maskable using the
dedicated bits in the core Status Register. Priority level 3 is non maskable. Depending on a
processor device, the INTC peripheral module enables up to 85 interrupt sources to be mapped to
selected priority level and provides the necessary interface to the processor core.
See MC56F83xx Core Reference Manual or Section 2.5 on page 2-24 of this document for more
information about interrupts and interrupt processing.
5.2.2

Quick Reference

This section is intended as a source of quick access information, while the details are discussed in
Section 5.2.3.
Module base address
INTC (INTC_BASE)
5.2.2.1

API Definition

The following header files are needed in order to use the INTC device driver:
Required Header File(s):
#include "qs.h"
#include "intc.h"
The following information may be found in the header file intc.h.
Public Data Structure(s):
none
FREESCALE SEMICONDUCTOR
Table 5-43. INTC Module Base Address
MC56F801x
of / for
0xF060
Targeting 56F8xxx Platform
MC56F802x/3x MC56F83xx
0xF0E0 0xF1A0
5-61