Boot Sequence - Freescale Semiconductor DSP56800E User Manual

Chapter 2
Core System Infrastructure
The Core System Infrastructure is one of the three main blocks that compose the
DSP56800E_Quick_Start tool (see Section 1.1.1 where the partitioning is described). Its purpose
is to provide the fundamental infrastructure for the 56800E device operation (e.g. sets the
operation mode, the interrupt handling, the initialization of the global variables, CodeWarrior
Compiler options). It also provides some additional support (commonly used macros, data types)
and enables further integration with On-chip Drivers.
2.1

Boot Sequence

The Core System Infrastructure provides the fundamental code which is executed before the
user's main function. This code provides basic settings needed to initialize the chip, settings
required by the CodeWarrior Compiler, initialization of global variables. Finally it passes control
to the user's application code (the main function).
Note: This chapter describes the boot process of the MC56F83xx family of microcontrollers
which contain the Boot Flash memory. The boot process of the devices without the dedicated
Boot Flash memory (MC56F80xx) is relatively simpler as the vector table need not to be
relocated. Except this difference, the other startup steps are common for all 56800E devices.
For the MC56F83xx devices, the post-reset execution flow may be briefly described as follows
(also see Figure 2-1):
1. After processor reset, the execution starts at the Hardware Reset vector in program memory,
where the DSP56800E_Quick_Start tool places its jump to the Start() assembly routine
— For the EXTBOOT=1 and EMI_MODE=0 processor configuration (processor external pins are
sampled during reset), the reset vector is located at address 0x0000 and the jump is supplied
directly from the first entry of vector table located in the interrupt_vectors section in vectors.c
file.
— For another configuration, the reset vector is located at address 0x20000. A jump to the Start()
routine is compiled on this address (in the boot_jump section in vectors.c file) while keeping
the full vector table on address 0x0000.
2. If the chip reset is generated by the watchdog module (COP), the same rules as in the
previous point apply, except that the second entry of the vector table is used. Again the COP
Reset vector is supplied from either the full vector table at address 0x0000
(interrupt_vectors section) or the reset jumps table at address 0x20000 (boot_jump
section). The default value of COP Reset vector is Start(), so the standard power-up code
is processed. The user is able to redefine the COP Reset service routine same way the other
interrupt vectors are installed (see Section 2.5.2 on page 2-27 for more details).
FREESCALE SEMICONDUCTOR Targeting 56F8xxx Platform 2-1