Wintc Driver; Introduction; Quick Reference; Api Definition - Freescale Semiconductor DSP56800E User Manual

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WINTC Driver

This section describes the API for the MC56F800x Interrupt Controller (WINTC) on-chip

module. The functionality of the WINTC module itself is described in the Data Sheets of each

particular device.

The MC56F800x interrupt system consists of the Interrupt unit in the processor core and of the

Interrupt Controller Module (WINTC). The processor core supports four interrupt priority levels

with hardware support for interrupt nesting. Priority levels 0-2 are maskable using the dedicated

bits in the core Status Register. Priority level 3 is non maskable. Depending on a processor device,

the WINTC peripheral module enables up to 85 interrupt sources. Peripheral interrupts are

mapped to priority level 0. Up to three level 0 peripheral interrupts can be re-assigned as level 1

interrupts: USER1, USER2 and USER3. When an interrupt is re-assigned, its original vector

becomes inactive, and the ISR address must be replaced in USER1/2/3 instead. In similar fasion,

up to three level 0 peripheral interrupts can be re-assigned as level 2 interrupts: USER4, USER5

and USER6. If activated, USER6 can act as a fast interrupt. See the 56F800x Peripheral

Reference Manual for more details.

This section is intended as a source of quick access information, while the details are discussed in

Section 5.3.3.

Module base address

WINTC (WINTC_BASE)

The following header files are needed in order to use the WINTC device driver:

Required Header File(s):

#include "qs.h"

#include "wintc.h"

The following information may be found in the header file wintc.h.

Public Data Structure(s):

FREESCALE SEMICONDUCTOR

Table 5-62. WINTC Module Base Address

Targeting 56F8xxx Platform

MC56F802x/3x

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