5 SETTINGS
Where:
Dp k ( )
Di k ( )
Dd k ( )
The PID regulator logic is shown below.
GE Multilin
p k ( ) p k 1
(
)
=
–
–
K br k ( ) y k ( )
(
br k 1
(
)
=
–
–
–
+
i k ( ) p k 1
(
)
=
–
–
KT
S
(
)
---------- -
AW w k 1 )
(
(
e k 1
=
–
+
–
T
i
d k ( ) d k 1
(
)
=
–
–
T
d
----------------------- -
Dd k 1
(
)
(
y k ( )
=
–
+
T
NT
+
d
S
Figure 5–43: PID REGULATOR LOGIC
C30 Controller System
y k 1
(
)
)
–
T
S
) v k 1
(
)
)
------
–
–
T
t
T
KN
d
----------------------- -
(
2y k 1
(
)
y k 2
(
)
)
)
–
–
+
–
T
NT
+
d
5.6 CONTROL ELEMENTS
(EQ 5.3)
S
5-109
5