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The access control unit is responsible for the selection of the on-chip memory resources.
The interrupt requests from the peripheral units are handled by the interrupt controller
unit.
2.3
SFRs of the CPU
The XC800 Core registers occupy direct Internal Data Memory space locations in the
range 80
to FF
.
H
H
2.3.1
Stack Pointer (SP, 81
The SP register contains the Stack Pointer. The Stack Pointer is used to load the
program counter into internal data memory during LCALL and ACALL instructions and
to retrieve the program counter from memory during RET and RETI instructions. Data
may also be saved on or retrieved from the stack using PUSH and POP instructions.
Instructions that use the stack automatically pre-increment or post-decrement the stack
pointer so that the stack pointer always points to the last byte written to the stack, i.e. the
top of the stack. On reset, the Stack Pointer is reset to 07
begin at a location = 08
software control. The programmer must ensure that the location and size of the stack in
internal data memory do not overlap with other application data.
2.3.2
Data Pointer (DPTR, 82-3
The Data Pointer (DPTR) is stored in registers DPL (Data Pointer Low byte) and DPH
(Data Pointer High byte) to form 16-bit addresses for External Data Memory accesses
(MOVX A,@DPTR and MOVX @DPTR,A), for program byte moves (MOVC
A,@A+DPTR) and for indirect program jumps (JMP @A+DPTR).
Two true 16-bit operations are allowed on the Data Pointer: load immediate
(MOV DPTR,#data) and increment (INC DPTR).
2.3.3
Accumulator (ACC, E0
This register provides one of the operands for most ALU operations. ACC is the symbol
for the accumulator register. The mnemonics for accumulator-specific instructions,
however, refer to the accumulator simply as "A".
2.3.4
B Register (F0
The B register is used during multiply and divide operations to provide the second
operand. For other instructions, it can be treated as another scratch pad register.
2.3.5
Program Status Word (PSW, D0
The PSW contains several status bits that reflect the current state of the core.
User's Manual
XC800 Core, V 1.0.2
)
H
above register bank zero. The SP can be read or written under
H
H
)
H
)
H
. This causes the stack to
H
)
)
H
2-3
XC82x
XC800 Core
V1.0, 2010-02
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