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B.5
Bounce Suppression
If an input signal is bouncing, the blocked bit (BL) is set. The number of state changes until the
BL bit is set, as well as the monitoring time during which the information must be static until
the BL bit is reset, are adjustable via constants. An output is set to
With an edge detection for the rising edge (R_TRIG_INEDRISE0) and the falling edge
(F_EDTIMEFALL0) the counter (CTU_EDC0) will be incremented by 1. At the same time the R
input of the counter is reset via an ON delay for the rising edge (TON_EDTIMERISE0) as well
as for the falling edge (TON_EDTIMEFALL0). With this function all state changes of the input
will be integrated by the counter (started with the first edge and triggered by each following
one).
As soon as a state change of the input happens the flag (M_BOOL_COUNTER00) is reset and
the input of an AND (module 8) is set (inverted). If the sum of state changes is greater as or
equal to a defined number (CV>=PV) the counter output is set as well, and the BL bit is set.
With the set BL bit the output is reset by another AND (module 9).
After termination of the monitoring time the R input of the counter is set again, and the counter
is reset. If the BL bit is set, it will be reset as well (output of module 8 is 0).
input
In the procession sequence the R input of the counter must be reset first, because only after-
wards the positive edge at the CU input of the counter causes an increment. Therefore the ap-
plication program handles the R input before the CU input of the counter.
SICAM RTUs, User Manual SICAM CMIC
DC8-001-2.09, Edition 08.2016
R_TRIGINEDRISE0
1
1
3
2
F_TRIG_INEDFALL0
Parameter
in the INIT part
TON_EDTIMERISE0
TON
1
4
6
TON
5
TON_EDTIMEFALL0
M_BOOL_MODULE03
CU
7
Q
counter
upward
M_BOOL_MODULE7
R
PV
CTU_FLZ0
M_BOOL_COUNTER00
Error Handling
0
during the BL bit is set.
&
blocked
8
&
output
9
327
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