Clocking; Introduction; Port Clocking Mode - IDT 89HPES64H16G2 User Manual

Notes
PES64H16G2 User Manual
®

Introduction

Figure 4.1 provides a logical representation of the PES64H16G2 clocking architecture. The
PES64H16G2 has a single differential global reference clock input (GCLK).
Port 0
SerDes
Quad
Port 0
Stack
PLL
GCLK
Figure 4.1 Logical Representation of the PES64H16G2 Clocking Architecture
The differential global reference clock input (GCLK) is driven into the device on the GCLKP[1:0] and
GCLKN[1:0] pins.
– The nominal frequency of the global reference clock input may be selected by the Global Clock
Frequency Select (GCLKFSEL) pin to be either 100 MHz or 125 MHz.
– Both global reference clock differential inputs should be driven with the same frequency. There
are no skew requirements between the GCLKP[0]/GCLKN[0] and GCLKP[1]/GCLKN[1] inputs.
Any constant phase difference is acceptable.
– The Global Clock supports Spread Spectrum Clocking (SSC).
– The global reference clock input is provided to each SerDes quad and to an on-chip PLL.
• The on-chip PLL uses this clock to generate a 250 MHz core clock that is used by internal switch
logic (e.g., switch core, portion of a stack, etc.).
• The PLL within each SerDes quad generates a 5.0 GHz clock used by the SerDes analog
portion (PMA) and a 250 MHz clock used by the digital portion (PCS).

Port Clocking Mode

Port clocking refers to the clock that a port uses to receive and transmit serial data. All ports in the switch
use the global reference clock (GCLK) input for receiving and transmitting serial data. The switch does not
introduce any requirements on the global reference clock input beyond those imposed by PCI express.
Depending on the system configuration, a port may employ the common Refclk or separate Refclk architec-
tures defined by the PCIe Base specification.
The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot
configuration vector as shown in Table 4.1. This field determines the initial value of the Slot Clock Configu-
ration (SCLK) field in each port's PCI Express Link Status (PCIELSTS) register. The SCLK field controls the
Port 1 Port 2
SerDes SerDes
Quad Quad
Port 1 Port 2
Stack Stack
Switch Core
4 - 1
Chapter 4

Clocking

Port 3 Port 14
SerDes SerDes
Quad Quad
...
Port 3 Port 14
Stack Stack
April 5, 2013
Port 15
SerDes
Quad
Port 15
Stack