Link Retraining - IDT 89HPES64H16G2 User Manual

IDT Link Operation
Notes
PES64H16G2 User Manual
As mentioned above, the Target Link Speed (TLS) field of the port's Link Control 2 Register
(PCIELCTL2) sets the preferred link speed. By default, the Target Link Speed of each PES64H16G2 port is
set to 5.0 GT/s. During normal operation, the link speed of a downstream port may be modified by setting
the TLS field of the port's PCIELCTL2 register to the desired speed and initiating link retraining by writing a
one to the Link Retrain (LRET) bit in the Link Control (PCIELCTL) register.
– The port will only initiate a change to a higher speed if the link partner advertised support for the
higher speed in its latest entry to the Configuration.Complete or Recovery.RcvrCfg states.
– If a speed change is initiated to a speed not supported by the link partner, then the port will remain
at the current speed by transitioning through the Recovery state without the "Speed_Change" bit
set.
Notification of link speed changes if provided through the link bandwidth notification mechanism
described in the PCIe specification. This mechanism is enabled by setting the Link Bandwidth Management
Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports. For downstream
ports, the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register is set when the link
speed is changed due to the following reasons:
– Link speed downgrade initiated by a PES64H16G2 port when the PHY layer cannot achieve reli-
able operation at the higher speed. Note that this does not include link speed downgrading due to
failure to achieve symbol lock while trying to upgrade link speed via the Recovery state.
– Link speed change initiated by the link partner that was not indicated as an autonomous change.
Also, the LBWSTS bit is set whenever software sets the LRET bit in the PCIELCTL register, even if the
link speed is not changed. Note that the LBWSTS bit is not set during the initial link speed change (i.e., the
speed change from Gen1 to Gen2 after fundamental reset or a full-link-retrain via the 'Detect' state). Soft-
ware can verify the link speed by reading the Current Link Speed (CLS) field of the port's Link Status
Register (PCIELSTS).

Link Retraining

Per the PCI Express 2.0 specification, link retraining can be done autonomously in response to link
problems (i.e., repeated TLP replay attempts), or as a result of software setting the link retrain (LRET) bit in
the PCI Express Link Control (PCIELCTL) register.
Writing a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTATE0) register of any
port forces that port's PCIe link to retrain. When this occurs, the LTSSM transitions directly to the Detect
state.
Link retraining does not result in the link going down, unless the LTSSM transitions through the Detect
state in its retraining attempt. The speed of the link is not necessarily changed as a result of link retraining.
A link that operates at 5.0 GT/s will continue to operate at that speed if the link retraining attempt is
successful at that speed. Else, the link speed is changed to 2.5 GT/s.
When link retraining results in the speed of the link being downgraded from 5.0 GT/s to 2.5 GT/s, the
Link Bandwidth Management Status (LBWSTS) bit is set in the PCI Express Link Status (PCIELSTS)
register. Additionally, the PHY LTSSM remains at the downgraded speed until the link partner requests a
link speed upgrade, software sets the LRET bit in the PCIELCTL register, or the link is fully retained via the
FLRET bit in the PHYLSTATE0 register.
In addition to link retrain (via the Recovery state), the link may be fully retrained by writing a one to the
Full Link Retrain (FLRET) bit in a port's Phy Link State 0 (PHYLSTATE0) register. When this occurs the
LTSSM transitions directly to the Detect state. This causes the data-link to go down (refer to the Link Down
section below).
Note that the LBWSTS bit in the PCIELSTS register is not affected by a full link retrain (i.e., since the
data-link transitioned to the DL_Down state).
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