Toshiba DP120F Service Manual page 369

• DMAC GA Signal Table (7/7)
No. Signal Name
177 MDTRQ1
179 WAITC
182-184 FC0-2
185 BGX
186 RWX
187 LDSX
188 UDSX
189 ASX
191-198, A0-23
200-207, 209,
211-216
218-225, D0-15
227-234
236-238 IPL0-2X
239 DTACKX
I: Input O: Output
DP120F/DP125F Circuit Description
Type
I Line 1 MODEM transmit data transfer request signal
The MODEM (IC5) makes a request to transfer trans-
mit data.
- +5V
I CPU operating status 0-2 signals
The CPU (IC66) indicates the operating status.
I Bus ground signal (active-low)
The CPU indicates release of the bus.
I Read/write signal (H: Read, L: Write)
I Lower address strobe signal (active-low)
Causes the lower data bus data to be latched.
I Upper address strobe signal (active-low)
Causes the upper data bus data to be latched.
I Address strobe signal (active-low)
Causes the address bus data to be latched.
I/O Address bus
I/O Data bus
O CPU interrupt request 0-2 signals (active-low)
Request the CPU for interruption.
O Data transfer acknowledge (active-low)
Indicates the end of data transfer to the CPU.
I/O: Bidirectional
Functions
7-60 March 2000 © TOSHIBA TEC