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Motorola Freescale Semiconductor DSP56000 Manuals
Manuals and User Guides for Motorola Freescale Semiconductor DSP56000. We have
3
Motorola Freescale Semiconductor DSP56000 manuals available for free PDF download: Manual, User Manual
Motorola Freescale Semiconductor DSP56000 Manual (637 pages)
24-bit Digital Signal Processor
Brand:
Motorola
| Category:
Signal Processors
| Size: 2.16 MB
Table of Contents
Table of Contents
3
Dsp56K Family Introduction
13
Section 1
14
Analog Signal Processing
15
Introduction
15
Section 1.1 Introduction
15
Origin of Digital Signal Processing
16
Section 1.2 Origin of Digital Signal Processing
16
DSP Hardware Origins
21
Summary of Dsp56K Family Features
21
Section 1.2 Summary of Dsp56K Family Features
21
Manual Organization
23
Section 1.3 Manual Organization
23
Dsp56K Central Architecture Overview
25
Overview
25
Section 2
26
Data Buses
27
Section 2.1 Dsp56K Central Architecture Overview
27
Section 2.2 Data Buses
27
Data Alu
27
Program Control Unit
27
Address Buses
28
Section 2.3 Address Buses
28
Address Generation Unit
29
Data Alu
29
Program Control Unit
29
Section 2.4 Data Alu
29
Section 2.5 Address Generation Unit
29
Section 2.6 Program Control Unit
29
Memory Expansion Port (Port A)
30
ON-CHIP EMULATOR (Once)
30
Phase-Locked Loop (Pll) Based Clocking
30
Section 2.7 Memory Expansion Port (Port A)
30
SECTION 2.8 ON-CHIP EMULATOR (Once)
30
Section 2.9 Phase-Locked Loop (Pll) Based Clocking
30
Data Arithmetic Logic Unit
31
Section 3
32
Section 3.1 Data Arithmetic Logic Unit
33
DSP56K Block Diagram
34
Data ALU Input Registers (X1, X0, Y1, Y0)
35
MAC and Logic Unit
36
Data ALU a and B Accumulators
37
Overview and Data Alu Architecture
34
Section 3.2 Overview and Data Alu Architecture
34
MAC Unit
37
DATA ALU Accumulator Registers
38
Accumulator Shifter
39
Data Shifter/Limiter
39
Limiting (Saturation Arithmetic)
39
Data Representation and Rounding
40
Scaling
40
Section 3.3 Data Representation and Rounding
40
Saturation Arithmetic
40
Integer-To-Fractional Data Conversion
41
Limited Data Values
41
Bit Weighting and Alignment of Operands
42
Integer/Fractional Number Comparison
43
Integer/Fractional Multiplication Comparison
44
Convergent Rounding
45
Double Precision Multiply Mode
46
Section 3.4 Double Precision Multiply Mode
46
Full Double Precision Multiply Algorithm
46
Data Alu Programming Model
49
Section 3.5 Data Alu Programming Model
49
DSP56K Programming Model
49
Data Alu Summary
50
Section 3.6 Data Alu Summary
50
Address Generation Unit
51
Section 4
52
Address Generation Unit and Addressing Modes
53
Agu Architecture
53
Section 4.1 Address Generation Unit and Addressing Modes
53
Section 4.2 Agu Architecture
53
Address Register Files (Rn)
53
Offset Register Files (Nn)
54
DSP56K Block Diagram
54
Modifier Register Files (Mn)
55
Address ALU
55
AGU Block Diagram
55
Programming Model
56
Address Output Multiplexers
56
Section 4.3 Programming Model
56
Address Register Files (R0 - R3 and R4 - R7)
57
Offset Register Files (N0 - N3 and N4 - N7)
57
AGU Programming Model
57
Address Register Indirect Summary
58
Address Register Indirect Modes
59
No Update
59
Postdecrement by 1
59
Postincrement by 1
59
Address Register Indirect — no Update
60
Postincrement by Offset Nn
60
Address Register Indirect — Postincrement
61
Postdecrement by Offset Nn
61
Address Register Indirect — Postdecrement
62
Indexed by Offset Nn
62
Address Register Indirect — Postincrement by Offset Nn
63
Predecrement by 1
63
Address Modifier Arithmetic Types
64
Address Register Indirect — Postdecrement by Offset Nn
64
Address Register Indirect — Indexed by Offset Nn
65
Address Register Indirect — Predecrement
66
Linear Modifier (Mn=$Ffff)
66
Modulo Modifier
67
Address Modifier Summary
68
Addressing
58
Modifier Register Files (M0 - M3 and M4 - M7)
58
Section 4.4 Addressing
58
Circular Buffer
69
Linear Addressing with a Modulo Modifier
70
Modulo Modifier Example
71
Reverse-Carry Modifier (Mn=$0000)
72
Bit-Reverse Addressing Sequence Example
73
Bit-Reverse Address Calculation Example
74
Address-Modifier-Type Encoding Summary
75
Address Modifier Summary
76
Program Control Unit
77
Section 5
78
Program Address Generator
79
Section 5.1 Program Control Unit
79
Section 5.2 Overview
79
Overview
80
DSP56K Block Diagram
80
Program Control Unit (Pcu) Architecture
81
Section 5.3 Program Control Unit (Pcu) Architecture
81
Program Address Generator (PAG)
81
Program Decode Controller
81
Instruction Pipeline Format
82
Program Interrupt Controller
82
Three-Stage Pipeline
83
Programming Model
84
Section 5.4 Programming Model
84
Program Counter
84
Status Register
85
Carry (Bit 0)
86
Negative (Bit 3)
86
Overflow (Bit 1)
86
Unnormalized (Bit 4)
86
Zero (Bit 2)
86
Extension (Bit 5)
87
Limit (Bit 6)
87
Scaling Bit (Bit 7)
87
Interrupt Masks (Bits 8 and 9)
88
Scaling Mode (Bits 10 and 11)
88
Double Precision Multiply Mode (Bit 14)
89
Reserved Status (Bit 12)
89
Trace Mode (Bit 13)
89
Loop Flag (Bit 15)
90
Operating Mode Register
90
System Stack
90
OMR Format
90
Stack Pointer (Bits 0-3)
91
Stack Pointer Register
91
Stack Error Flag (Bit 4)
92
SP Register Values
92
Loop Address Register
93
Loop Counter Register
93
Programming Model Summary
93
Reserved Stack Pointer Registration (Bits 6-23)
93
Underflow Flag (Bit 5)
93
DSP56K Central Processing Module Programming Model
94
Instruction Set Introduction
95
Section 6
96
Syntax
97
Section 6.1 Instruction Set Introduction
97
Section 6.2 Syntax
97
Instruction Formats
98
Section 6.3 Instruction Formats
98
DSP56K Central Processing Module Programming Model
98
Operand Sizes
99
General Format of an Instruction Operation Word
99
Data ALU Registers
100
Data Organization in Registers
100
Operand Sizes
100
AGU Registers
101
Reading and Writing the ALU Extension Registers
101
Reading and Writing the Address ALU Registers
101
Program Control Registers
102
Reading and Writing Control Registers
102
Data Organization in Memory
103
Memory References
105
Operand References
105
Program References
105
Register References
105
Stack References
105
Addressing Modes
107
L Memory References
107
Y Memory References
107
YX Memory References
107
Address Register Direct
108
Address Register Indirect Modes
108
Data or Control Register Direct
108
Register Direct Modes
108
Absolute Address
109
Immediate Data
109
Immediate Short
109
Short Jump Address
109
Special Addressing Modes
109
Special Addressing – Immediate Data
110
Absolute Short
111
Addressing Modes Summary
111
I/O Short
111
Implicit Reference
111
Special Addressing – Absolute Addressing
111
Instruction Groups
113
Special Addressing – Short Jump Address
113
Special Addressing – Absolute Short Address
114
Section 6.4 Instruction Groups
115
Arithmetic Instructions
115
Special Addressing – I/O Short Address
115
Logical Instructions
117
Bit Manipulation Instructions
119
Loop Instructions
119
Hardware DO Loop
119
Move Instructions
121
Nested DO Loops
121
Classifications of Parallel Data Moves
121
Program Control Instructions
122
Parallel Move Examples
122
Processing States
125
Section 7
126
Instruction Pipelining
127
Section 7.1 Processing States
127
Section 7.2 Normal Processing State
127
Instruction Pipeline
127
Normal Processing State
128
Summary of Pipeline-Related Restrictions
132
Exception Processing State (Interrupt Processing)
134
Section 7.3 Exception Processing State
134
Interrupt Types
135
Interrupt Priority Structure
136
Fast and Long Interrupt Examples
137
Exception Priorities Within an IPL
138
Interrupt Priority Levels
138
Interrupt Priority Register (Addr X:$FFFF)
138
Status Register Interrupt Mask Bits
138
Interrupt Sources
139
Central Processor Interrupt Priorities Within an IPL
139
Hardware Interrupt Sources
140
Interrupting an SWI
141
Software Interrupt Sources
142
Illegal Instruction Interrupt Serviced by a Fast Interrupt
143
Illegal Instruction Interrupt Serviced by a Long Interrupt
144
Repeated Illegal Instruction
145
Other Interrupt Sources
146
Trace Exception
147
Interrupt Arbitration
148
Interrupt Instruction Fetch
148
Instructions Preceding the Interrupt Instruction Fetch
149
Interrupt Instruction Execution
150
Fast Interrupt Service Routine
151
Two Consecutive Fast Interrupts
152
Long Interrupt Service Routine
154
JSR First Instruction of a Fast Interrupt
155
JSR Second Instruction of a Fast Interrupt
156
External Interrupt
139
Interrupt Priority Level Bits
139
Reset Processing State
157
Section 7.4 Reset Processing State
157
Interrupting an REP Instruction
158
Interrupting Sequential REP Instructions
159
Wait Processing State
160
Section 7.5 Wait Processing State
160
Wait Instruction Timing
160
Stop Processing State
161
Simultaneous Wait Instruction and Interrupt
161
STOP Instruction Sequence
162
STOP Instruction Sequence Followed by IRQA
163
STOP Instruction Sequence Recovering with RESET
166
Port a Interface
170
Port a Interface
171
Port a Signals
171
Port a Interface
172
Port a Overview
171
Pll Clock Oscillator
177
Section 8
178
Pll Components
178
Pll Clock Oscillator Introduction
179
Pll Components
179
Section 9.1 Pll Clock Oscillator Introduction
179
Section 9.2 Pll Components
180
Phase Detector and Charge Pump Loop Filter
180
Frequency Multiplier
181
Low Power Divider (LPD)
181
PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11
181
PLL Control Register (PCTL)
181
Voltage Controlled Oscillator (VCO)
181
Multiplication Factor Bits MF0-MF11
181
PCTL Division Factor Bits (DF0-DF3) - Bits 12-15
182
Division Factor Bits DF0-DF3
182
PCTL XTAL Disable Bit (XTLD) - Bit 16
183
PCTL STOP Processing State Bit (PSTP) - Bit 17
183
PCTL Clock Output Disable Bits (COD0-COD1) - Bits 19-20
184
PCTL PLL Enable Bit (PEN) - Bit 18
184
Clock Output Disable Bits COD0-COD1
184
PSTP and PEN Relationship
184
Pll Pins
185
PCTL Chip Clock Source Bit (CSRC) - Bit 21
185
PCTL Reserved Bit - Bit 23
185
Section 9.3 Pll Pins
185
Pll Operation Considerations
187
Section 9.4 Pll Operation Considerations
187
Hardware Reset
187
Operating Frequency
187
Change of DF0-DF3 Bits
188
Changing the MF0-MF11 Bits
188
Operation with PLL Disabled
188
CKOUT Considerations
189
Loss of Lock
189
STOP Processing State
189
Synchronization Among EXTAL, CKOUT, and the Internal Clock
190
ON-CHIP EMULATION (Once)
191
Section 9
192
ON-CHIP EMULATION (Once) PINS
193
Section 10.1 Introduction
193
SECTION 10.2 ON-CHIP EMULATION (Once) PINS
193
On-Chip Emulation Introduction
193
Once Block Diagram
193
DSP56K Block Diagram
194
Chip Status Information
195
Once CONTROLLER and SERIAL INTERFACE
196
SECTION 10.3 Once CONTROLLER and SERIAL INTERFACE
196
Once Command Register
197
Once Register Addressing
197
Once Status and Control Register (OSCR)
199
Memory Breakpoint Control Table
200
Once MEMORY BREAKPOINT LOGIC
201
SECTION 10.4 Once MEMORY BREAKPOINT LOGIC
201
Once Memory Breakpoint Logic
202
Once TRACE LOGIC
203
SECTION 10.5 Once TRACE LOGIC
203
Once Trace Logic Block Diagram
204
Methods of Entering the Debug Mode
205
Section 10.6 Methods of Entering the Debug Mode
205
Pipeline Information and Global Data Bus Register
206
Section 10.7 Pipeline Information and Global Data Bus Register
206
Once Pipeline Information and GDB Registers
207
Program Address Bus History Buffer
207
Section 10.8 Program Address Bus History Buffer
207
Once PAB FIFO
208
Serial Protocol Description
209
Section 10.9 Serial Protocol Description
209
Dsp56K Target Site Debug System Requirements
210
Section 10.10 Dsp56K Target Site Debug System Requirements
210
USING the Once
211
SECTION 10.11 USING the Once
211
Section 10
220
Additional Support
221
User Support
221
Section 11.1 User Support
221
Motorola Dsp Product Support
222
Dsp56000Clasx Assembler/Simulator
222
Macro Cross Assembler Features
222
Section 11.2 Motorola Dsp Product Support
222
Dsp56Kccx Language Compiler Features
223
Simulator Features
223
Dsp56Kadsx APPLICATION DEVELOPMENT SYSTEM
224
DSP56KADS Application Development
224
Dsp56Kadsx Application Development
224
SECTION 11.3 Dsp56Kadsx APPLICATION DEVELOPMENT SYSTEM
224
System Hardware Features
224
System Software Features
224
Dr. Bub ELECTRONIC BULLETIN BOARD
225
SECTION 11.4 Dr. Bub ELECTRONIC BULLETIN BOARD
225
Support Integrated Circuits
225
Motorola Dsp News
234
Motorola Field Application Engineers
234
Design Hotline– 1-800-521-6274
234
Section 11.5 Motorola Dsp News
234
Section 11.6 Motorola Field Application Engineers
234
Dsp Help Line – (512) 891-3230
234
Marketing Information– (512) 891-2030
234
Third-Party Support Information – (512) 891-3098
234
University Support – (512) 891-3098
234
TRAINING COURSES – (602) 897-3665 or (800) 521-6274
235
Reference Books and Manuals
235
Section 11.13 Reference Books and Manuals
236
Section 11
244
Appendix A Introduction
245
Introduction
245
Third Party Support
245
Motorola Dsp Product Support
246
Support Integrated Circuits
248
Motorola Dsp News
249
Motorola Field Application Engineers
249
Dsp Applications Help Line - (512) 891-3230
249
Design Hotline - 1-800-521-6274
249
Dsp Marketing Information - (512) 891-2030
249
Dsp Third-Party Support Information - (512) 891-3098
249
Dsp University Support - (512) 891-3098
249
DSP TRAINING COURSES - (602) 897-3665 or (800) 521-6274
250
Dr. Bub ELECTRONIC BULLETIN BOARD
250
Reference Books and Manuals
259
Section 12
268
Instruction Guide
269
Section A.1 Appendix A Introduction
269
Section A.2 Instruction Guide
269
Notation
270
Section A.3 Notation
270
A-1 Instruction Description Notation
271
Addressing Modes
276
Section A.4 Addressing Modes
276
A-2 DSP56K Addressing Modes
277
A-3 DSP56K Addressing Mode Encoding
278
Addressing Mode Modifiers
279
A-4 Addressing Mode Modifier Summary
280
Condition Code Computation
281
Section A.5 Condition Code Computation
281
Condition Code Computation Table A-5 Condition Code Computations for Instructions (no Parallel Move)
285
A-5 Condition Code Computations for Instructions (no Parallel Move)
285
Parallel Move Descriptions
286
Section A.6 Parallel Move Descriptions
286
Instruction Descriptions
287
Section A.7 Instruction Descriptions
287
Adc
290
Add
292
Addl
294
Addr
296
And
298
Andi
300
Asl
302
Asr
304
Bchg
306
Bclr
314
Bset
322
Btst
330
Clr
336
Cmpm
340
Debug
342
Debugcc
344
Dec
346
DIV
348
Enddo
364
Eor
366
Illegal
368
Jmp
382
Jscc
384
Jsclr
389
Jset
396
Jsr
402
Jsset
405
Lsl
410
Lsr
412
A.8 Instruction Timing
560
A-6 Instruction Timing Summary
567
A-7 Parallel Data Move Timing
568
A-8 MOVEC Timing Summary
568
A-9 MOVEP Timing Summary
568
A-10 Bit Manipulation Timing Summary
569
A-11 Jump Instruction Timing Summary
569
A-12 RTI/RTS Timing Summary
570
A-13 Addressing Mode Timing Summary
570
A.9 Instruction Sequence Restrictions
571
A-14 Memory Access Timing Summary
571
A.10 Instruction Encoding
577
A-15 Single-Bit Register Encodings
578
A-16 Single-Bit Special Register Encodings
578
A-17 Double-Bit Register Encodings
578
A-18 Triple-Bit Register Encodings
579
A-19 (A)Four-Bit Register Encodings for 12 Registers in Data ALU
579
A-19 (B)Four-Bit Register Encodings for 16 Condition Codes
579
A-21 Six-Bit Register Encodings for 43 Registers On-Chip
580
A-22 Write Control Encoding
580
A-23 Memory Space Bit Encoding
580
Data ALU and Address ALU
580
A-25 Condition Code and Address Encoding
581
B.1 Introduction
607
B.2 Benchmark Programs
607
B-1 27-Mhz Benchmark Results for the DSP56001R27
608
B-1 20-Tap FIR Filter Example
610
B-2 Radix 2, In-Place, Decimation-In-Time FFT
614
B-5 Real Input FFT Based on Glenn Bergland Algorithm
616
Advertisement
Motorola Freescale Semiconductor DSP56000 Manual (596 pages)
24-BIT DIGITAL SIGNAL PROCESSOR
Brand:
Motorola
| Category:
Signal Processors
| Size: 3.37 MB
Table of Contents
Table of Contents
6
Dsp56K Family Introduction
16
Section 1
17
Analog Signal Processing
18
Introduction
18
Section 1.1 Introduction
18
Origin of Digital Signal Processing
19
Section 1.2 Origin of Digital Signal Processing
19
DSP Hardware Origins
24
Summary of Dsp56K Family Features
24
Section 1.2 Summary of Dsp56K Family Features
24
Manual Organization
26
Section 1.3 Manual Organization
26
Dsp56K Central Architecture Overview
28
Overview
28
Section 2
29
Data Buses
30
Section 2.1 Dsp56K Central Architecture Overview
30
Section 2.2 Data Buses
30
Data Alu
30
Program Control Unit
30
Address Buses
31
Section 2.3 Address Buses
31
Address Generation Unit
32
Data Alu
32
Program Control Unit
32
Section 2.4 Data Alu
32
Section 2.5 Address Generation Unit
32
Section 2.6 Program Control Unit
32
Memory Expansion Port (Port A)
33
ON-CHIP EMULATOR (Once)
33
Phase-Locked Loop (Pll) Based Clocking
33
Section 2.7 Memory Expansion Port (Port A)
33
SECTION 2.8 ON-CHIP EMULATOR (Once)
33
Section 2.9 Phase-Locked Loop (Pll) Based Clocking
33
Data Arithmetic Logic Unit
34
Section 3
35
Section 3.1 Data Arithmetic Logic Unit
36
DSP56K Block Diagram
37
Data ALU Input Registers (X1, X0, Y1, Y0)
38
MAC and Logic Unit
39
Data ALU a and B Accumulators
40
Overview and Data Alu Architecture
37
Section 3.2 Overview and Data Alu Architecture
37
MAC Unit
40
DATA ALU Accumulator Registers
41
Accumulator Shifter
42
Data Shifter/Limiter
42
Limiting (Saturation Arithmetic)
42
Data Representation and Rounding
43
Scaling
43
Section 3.3 Data Representation and Rounding
43
Saturation Arithmetic
43
Integer-To-Fractional Data Conversion
44
Limited Data Values
44
Bit Weighting and Alignment of Operands
45
Integer/Fractional Number Comparison
46
Integer/Fractional Multiplication Comparison
47
Convergent Rounding
48
Double Precision Multiply Mode
49
Section 3.4 Double Precision Multiply Mode
49
Full Double Precision Multiply Algorithm
49
Data Alu Programming Model
52
Section 3.5 Data Alu Programming Model
52
DSP56K Programming Model
52
Data Alu Summary
53
Section 3.6 Data Alu Summary
53
Address Generation Unit
54
Section 4
55
Address Generation Unit and Addressing Modes
56
Agu Architecture
56
Section 4.1 Address Generation Unit and Addressing Modes
56
Section 4.2 Agu Architecture
56
Address Register Files (Rn)
56
Offset Register Files (Nn)
57
DSP56K Block Diagram
57
Modifier Register Files (Mn)
58
Address ALU
58
AGU Block Diagram
58
Programming Model
59
Address Output Multiplexers
59
Section 4.3 Programming Model
59
Address Register Files (R0 - R3 and R4 - R7)
60
Offset Register Files (N0 - N3 and N4 - N7)
60
AGU Programming Model
60
Address Register Indirect Summary
61
Address Register Indirect Modes
62
No Update
62
Postdecrement by 1
62
Postincrement by 1
62
Address Register Indirect — no Update
63
Postincrement by Offset Nn
63
Address Register Indirect — Postincrement
64
Postdecrement by Offset Nn
64
Address Register Indirect — Postdecrement
65
Indexed by Offset Nn
65
Address Register Indirect — Postincrement by Offset Nn
66
Predecrement by 1
66
Address Modifier Arithmetic Types
67
Address Register Indirect — Postdecrement by Offset Nn
67
Address Register Indirect — Indexed by Offset Nn
68
Address Register Indirect — Predecrement
69
Linear Modifier (Mn=$Ffff)
69
Modulo Modifier
70
Addressing
61
Modifier Register Files (M0 - M3 and M4 - M7)
61
Section 4.4 Addressing
61
Address Modifier Summary
71
Circular Buffer
72
Linear Addressing with a Modulo Modifier
73
Modulo Modifier Example
74
Reverse-Carry Modifier (Mn=$0000)
75
Bit-Reverse Addressing Sequence Example
76
Bit-Reverse Address Calculation Example
77
Address-Modifier-Type Encoding Summary
78
Address Modifier Summary
79
Program Control Unit
80
Section 5
81
Program Address Generator
82
Section 5.1 Program Control Unit
82
Section 5.2 Overview
82
Overview
83
DSP56K Block Diagram
83
Program Control Unit (Pcu) Architecture
84
Section 5.3 Program Control Unit (Pcu) Architecture
84
Program Address Generator (PAG)
84
Program Decode Controller
84
Instruction Pipeline Format
85
Program Interrupt Controller
85
Three-Stage Pipeline
86
Programming Model
87
Section 5.4 Programming Model
87
Program Counter
87
Status Register
88
Carry (Bit 0)
89
Negative (Bit 3)
89
Overflow (Bit 1)
89
Unnormalized (Bit 4)
89
Zero (Bit 2)
89
Extension (Bit 5)
90
Limit (Bit 6)
90
Scaling Bit (Bit 7)
90
Interrupt Masks (Bits 8 and 9)
91
Scaling Mode (Bits 10 and 11)
91
Double Precision Multiply Mode (Bit 14)
92
Reserved Status (Bit 12)
92
Trace Mode (Bit 13)
92
Loop Flag (Bit 15)
93
Operating Mode Register
93
System Stack
93
OMR Format
93
Stack Pointer (Bits 0-3)
94
Stack Pointer Register
94
Stack Error Flag (Bit 4)
95
SP Register Values
95
Loop Address Register
96
Loop Counter Register
96
Programming Model Summary
96
Reserved Stack Pointer Registration (Bits 6-23)
96
Underflow Flag (Bit 5)
96
DSP56K Central Processing Module Programming Model
97
Instruction Set Introduction
98
Section 6
99
Syntax
100
Section 6.1 Instruction Set Introduction
100
Section 6.2 Syntax
100
Instruction Formats
101
Section 6.3 Instruction Formats
101
DSP56K Central Processing Module Programming Model
101
Operand Sizes
102
General Format of an Instruction Operation Word
102
Data ALU Registers
103
Data Organization in Registers
103
Operand Sizes
103
AGU Registers
104
Reading and Writing the ALU Extension Registers
104
Reading and Writing the Address ALU Registers
104
Program Control Registers
105
Reading and Writing Control Registers
105
Data Organization in Memory
106
Memory References
108
Operand References
108
Program References
108
Register References
108
Stack References
108
Addressing Modes
110
L Memory References
110
Y Memory References
110
YX Memory References
110
Address Register Direct
111
Address Register Indirect Modes
111
Data or Control Register Direct
111
Register Direct Modes
111
Absolute Address
112
Immediate Data
112
Immediate Short
112
Short Jump Address
112
Special Addressing Modes
112
Special Addressing – Immediate Data
113
Absolute Short
114
Addressing Modes Summary
114
I/O Short
114
Implicit Reference
114
Special Addressing – Absolute Addressing
114
Instruction Groups
116
Special Addressing – Short Jump Address
116
Special Addressing – Absolute Short Address
117
Section 6.4 Instruction Groups
118
Arithmetic Instructions
118
Special Addressing – I/O Short Address
118
Logical Instructions
120
Bit Manipulation Instructions
122
Loop Instructions
122
Hardware DO Loop
122
Move Instructions
124
Nested DO Loops
124
Classifications of Parallel Data Moves
124
Program Control Instructions
125
Parallel Move Examples
125
Processing States
128
Section 7
129
Instruction Pipelining
130
Section 7.1 Processing States
130
Section 7.2 Normal Processing State
130
Instruction Pipeline
130
Normal Processing State
131
Summary of Pipeline-Related Restrictions
135
Exception Processing State (Interrupt Processing)
137
Section 7.3 Exception Processing State
137
Interrupt Types
138
Interrupt Priority Structure
139
Fast and Long Interrupt Examples
140
Exception Priorities Within an IPL
141
Interrupt Priority Levels
141
Interrupt Priority Register (Addr X:$FFFF)
141
Status Register Interrupt Mask Bits
141
Interrupt Sources
142
Central Processor Interrupt Priorities Within an IPL
142
Hardware Interrupt Sources
143
Interrupting an SWI
144
Software Interrupt Sources
145
Illegal Instruction Interrupt Serviced by a Fast Interrupt
146
Illegal Instruction Interrupt Serviced by a Long Interrupt
147
Repeated Illegal Instruction
148
Other Interrupt Sources
149
Trace Exception
150
Interrupt Arbitration
151
Interrupt Instruction Fetch
151
Instructions Preceding the Interrupt Instruction Fetch
152
Interrupt Instruction Execution
153
Fast Interrupt Service Routine
154
Two Consecutive Fast Interrupts
155
Long Interrupt Service Routine
157
JSR First Instruction of a Fast Interrupt
158
JSR Second Instruction of a Fast Interrupt
159
External Interrupt
142
Interrupt Priority Level Bits
142
Reset Processing State
160
Section 7.4 Reset Processing State
160
Interrupting an REP Instruction
161
Interrupting Sequential REP Instructions
162
Wait Processing State
163
Section 7.5 Wait Processing State
163
Wait Instruction Timing
163
Stop Processing State
164
Simultaneous Wait Instruction and Interrupt
164
STOP Instruction Sequence
165
STOP Instruction Sequence Followed by IRQA
166
STOP Instruction Sequence Recovering with RESET
169
Port a Interface
173
Port a Interface
174
Port a Signals
174
Port a Interface
175
Port a Overview
174
Pll Clock Oscillator
180
Section 8
181
Pll Components
181
Pll Clock Oscillator Introduction
182
Pll Components
182
Section 9.1 Pll Clock Oscillator Introduction
182
Section 9.2 Pll Components
183
Phase Detector and Charge Pump Loop Filter
183
Frequency Multiplier
184
Low Power Divider (LPD)
184
PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11
184
PLL Control Register (PCTL)
184
Voltage Controlled Oscillator (VCO)
184
Multiplication Factor Bits MF0-MF11
184
Division Factor Bits DF0-DF3
185
PCTL XTAL Disable Bit (XTLD) - Bit 16
186
PCTL STOP Processing State Bit (PSTP) - Bit 17
186
PCTL Clock Output Disable Bits (COD0-COD1) - Bits 19-20
187
PCTL PLL Enable Bit (PEN) - Bit 18
187
Clock Output Disable Bits COD0-COD1
187
PSTP and PEN Relationship
187
Pll Pins
188
PCTL Chip Clock Source Bit (CSRC) - Bit 21
188
PCTL Reserved Bit - Bit 23
188
Section 9.3 Pll Pins
188
Pll Operation Considerations
190
Section 9.4 Pll Operation Considerations
190
Hardware Reset
190
Operating Frequency
190
Change of DF0-DF3 Bits
191
Changing the MF0-MF11 Bits
191
Operation with PLL Disabled
191
CKOUT Considerations
192
Loss of Lock
192
STOP Processing State
192
Synchronization Among EXTAL, CKOUT, and the Internal Clock
193
ON-CHIP EMULATION (Once)
194
Section 9
195
ON-CHIP EMULATION (Once) PINS
196
Section 10.1 Introduction
196
SECTION 10.2 ON-CHIP EMULATION (Once) PINS
196
On-Chip Emulation Introduction
196
Once Block Diagram
196
DSP56K Block Diagram
197
Chip Status Information
198
Once CONTROLLER and SERIAL INTERFACE
199
SECTION 10.3 Once CONTROLLER and SERIAL INTERFACE
199
Once Command Register
200
Once Register Addressing
200
Once Status and Control Register (OSCR)
202
Memory Breakpoint Control Table
203
Once MEMORY BREAKPOINT LOGIC
204
SECTION 10.4 Once MEMORY BREAKPOINT LOGIC
204
Once Memory Breakpoint Logic
205
Once TRACE LOGIC
206
SECTION 10.5 Once TRACE LOGIC
206
Once Trace Logic Block Diagram
207
Methods of Entering the Debug Mode
208
Section 10.6 Methods of Entering the Debug Mode
208
Pipeline Information and Global Data Bus Register
209
Section 10.7 Pipeline Information and Global Data Bus Register
209
Once Pipeline Information and GDB Registers
210
Program Address Bus History Buffer
210
Section 10.8 Program Address Bus History Buffer
210
Once PAB FIFO
211
Serial Protocol Description
212
Section 10.9 Serial Protocol Description
212
Dsp56K Target Site Debug System Requirements
213
Section 10.10 Dsp56K Target Site Debug System Requirements
213
USING the Once
214
SECTION 10.11 USING the Once
214
Section 10
223
Additional Support
224
User Support
224
Section 11.1 User Support
224
Motorola Dsp Product Support
225
Dsp56000Clasx Assembler/Simulator
225
Macro Cross Assembler Features
225
Section 11.2 Motorola Dsp Product Support
225
Dsp56Kccx Language Compiler Features
226
Simulator Features
226
Dsp56Kadsx APPLICATION DEVELOPMENT SYSTEM
227
DSP56KADS Application Development
227
Dsp56Kadsx Application Development
227
SECTION 11.3 Dsp56Kadsx APPLICATION DEVELOPMENT SYSTEM
227
System Hardware Features
227
System Software Features
227
Dr. Bub ELECTRONIC BULLETIN BOARD
228
SECTION 11.4 Dr. Bub ELECTRONIC BULLETIN BOARD
228
Support Integrated Circuits
228
Motorola Dsp News
237
Motorola Field Application Engineers
237
Design Hotline– 1-800-521-6274
237
Section 11.5 Motorola Dsp News
237
Section 11.6 Motorola Field Application Engineers
237
Dsp Help Line – (512) 891-3230
237
Marketing Information– (512) 891-2030
237
Third-Party Support Information – (512) 891-3098
237
University Support – (512) 891-3098
237
TRAINING COURSES – (602) 897-3665 or (800) 521-6274
238
Reference Books and Manuals
238
Section 11.13 Reference Books and Manuals
239
Section 11
247
Appendix A Introduction
248
Introduction
248
Third Party Support
248
Motorola Dsp Product Support
249
Support Integrated Circuits
251
Motorola Dsp News
252
Motorola Field Application Engineers
252
Dsp Applications Help Line - (512) 891-3230
252
Design Hotline - 1-800-521-6274
252
Dsp Marketing Information - (512) 891-2030
252
Dsp Third-Party Support Information - (512) 891-3098
252
Dsp University Support - (512) 891-3098
252
DSP TRAINING COURSES - (602) 897-3665 or (800) 521-6274
253
Dr. Bub ELECTRONIC BULLETIN BOARD
253
Reference Books and Manuals
262
Section 12
271
A.1 Appendix A Introduction
271
A.2 Instruction Guide
271
Instruction Guide
272
Section A.1 Appendix A Introduction
272
Section A.2 Instruction Guide
272
Notation
273
Section A.3 Notation
273
Addressing Modes
279
Section A.4 Addressing Modes
279
Addressing Mode Modifiers
282
Condition Code Computation
284
Section A.5 Condition Code Computation
284
Condition Code Computation Table A-5 Condition Code Computations for Instructions (no Parallel Move)
288
Parallel Move Descriptions
289
Section A.6 Parallel Move Descriptions
289
Instruction Descriptions
290
Section A.7 Instruction Descriptions
290
Adc
293
Add
295
Addl
297
Addr
299
And
301
Andi
303
Asl
305
Asr
307
Bchg
309
Bclr
317
Bset
325
Btst
333
Clr
339
Cmpm
343
Debug
345
Debugcc
347
Dec
349
DIV
351
Enddo
367
Eor
369
Illegal
371
Jmp
385
Jscc
387
Jsclr
392
Jset
399
Jsr
405
Jsset
408
Lsl
413
Lsr
415
B.1 Introduction
565
B.2 Benchmark Programs
565
B-1 27-Mhz Benchmark Results for the DSP56001R27
566
B-1 20-Tap FIR Filter Example
568
B-2 Radix 2, In-Place, Decimation-In-Time FFT
572
B-5 Real Input FFT Based on Glenn Bergland Algorithm
574
Motorola Freescale Semiconductor DSP56000 User Manual (126 pages)
Brand:
Motorola
| Category:
Signal Processors
| Size: 0.92 MB
Table of Contents
Addressing Modes
2
Binary Operators
5
Other Symbols
7
Addressing Mode Modifiers
10
Condition Code Computation
10
Parallel Move Descriptions
11
Instruction Descriptions
11
Instruction Format
107
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