Page Number List For Ihpc Memory Mapped Register Descriptions; Slot Enable - Intel 460GX Software Developer’s Manual

WXB Hot-Plug
8.2.1 Page Number List for IHPC Memory Mapped Register
Descriptions
8.2.2

Slot Enable

Address Offset:
Default Value:
Used to power-on a slot and connect it to the bus (or disconnect and power-down). The SOGO bit
must be set to start the output sequence. The set of usable Enable Slot bits is determined by the
strapping values on the P(A,B)HSIL, P(A,B)HSOL, and P(A,B)HSOC inputs. Unsupported slots in
a system do not have writeable Enable Slot bits. Writing a zero to a Enable Slot bit will clear the
associated Slot Power register bit.
Bits
7:6
5
4
3
2
1
0
8-12
Register
Extended Hot-Plug Miscellaneous................................................................ 8-18
LED Control.................................................................................................. 8-13
General Purpose Output ................................................................................ 8-17
Hot-Plug Interrupt and Clear......................................................................... 8-14
Hot-Plug Interrupt Mask ............................................................................... 8-15
Hot-Plug Miscellaneous................................................................................ 8-13
Hot-Plug Non-interrupt Inputs...................................................................... 8-17
Hot-Plug Slot Identifier................................................................................. 8-17
Hot-Plug Switch Interrupt Redirect Enable .................................................. 8-18
Serial Input Byte Data................................................................................... 8-16
Serial Input Byte Pointer............................................................................... 8-17
Slot Enable .................................................................................................... 8-12
Slot Power Control........................................................................................ 8-18
01h Size:
00h Attribute:
Description
reserved(0)
Enable Slot F
When 1, Slot F is powered and connected to the PCI bus
Enable Slot E
When 1, Slot E is powered and connected to the PCI bus
Enable Slot D
When 1, Slot D is powered and connected to the PCI bus
Enable Slot C
When 1, Slot C is powered and connected to the PCI bus
Enable Slot B
When 1, Slot B is powered and connected to the PCI bus
Enable Slot A
When 1, Slot A is powered and connected to the PCI bus
8 bits
Partial Read/Write (Pwr Good Rst Only)
Intel® 460GX Chipset Software Developer's Manual
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