3
System Architecture ........................................................................................................3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4
System Address Map ......................................................................................................4-1
4.1
4.2
4.3
4.4
5
Memory Subsystem ........................................................................................................5-1
5.1
5.2
5.3
5.4
5.5
6
6.1
iv
Coherency..........................................................................................................3-1
3.1.1
Processor Coherency............................................................................3-1
3.1.2
PCI Coherency......................................................................................3-2
3.1.3
AGP Coherency ....................................................................................3-2
Ordering .............................................................................................................3-2
WXB Arbitration..................................................................................................3-3
Big-endian Support ............................................................................................3-4
Indivisible Operations.........................................................................................3-4
3.6.1
Processor Locks....................................................................................3-4
3.6.2
Inbound PCI Locks................................................................................3-5
3.6.3
Atomic Writes ........................................................................................3-5
3.6.4
Atomic Reads ........................................................................................3-5
3.6.5
Interrupt Delivery................................................................................................3-6
3.8.1
3.8.2
Memory Map ......................................................................................................4-1
4.1.1
Compatibility Region .............................................................................4-1
4.1.2
4.1.3
4.1.4
4.1.5
I/O Address Map ................................................................................................4-5
Organization.......................................................................................................5-1
5.1.1
DIMM Types ..........................................................................................5-3
5.2.1
5.2.2
Bandwidth ..........................................................................................................5-5
Supporting Features...........................................................................................5-6
5.5.1
Auto Detection.......................................................................................5-6
5.5.2
Removing a Bad Row ...........................................................................5-6
5.5.3
5.5.4
Memory Scrubbing ................................................................................5-7
Integrity ..............................................................................................................6-1
6.1.1
System Bus ...........................................................................................6-1
6.1.2
DRAM....................................................................................................6-2
6.1.3
Expander Buses ....................................................................................6-2
6.1.4
PCI Buses .............................................................................................6-2
6.1.5
AGP.......................................................................................................6-2
Intel® 460GX Chipset System Software Developer's Manual