Intel 460GX Software Developer’s Manual page 34

Register Descriptions
2.4.2.11 DED1_ECC_FERR: ECC on First Memory Card A DED
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the ECC checkbits corresponding to the first DED detected by
memory interface 0 in the SDC.
Bits
7:0
2.4.2.12 DED1_TXINFO_FERR: TXINFO on First Memory Card A DED
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first DED detected by
memory interface 1 in the SDC.
Bits
15:9
8:6
5:0
2.4.2.13 SDC_FERR: First Error Status Register
Bus CBN, Device Number: 04h
Address Offset:
Default Value:
This register records the first error condition detected in the SDC. Writing a '1' to this register will
clear the bit in both SDC_FERR and the same bit in SDC_NERR.
Bits
31
30
29
28
27
2-14
04h
78h
00h
Description
ECC - ECC of Error.
04h
79-7Ah
00h
Description
reserved(0)
DC - Data Chunk of ITID.
ITID - ITID of error.
80-83h
0000h
Description
Simultaneous S/W write-one-to-clear and H/W error detected in the same cycle. This bit
will only be set if another bit is also set. This implies that the ERROR>_<TYPE>_FERR
data registers associated with the other asserted bit contain stale data.
PDB Receive Length Error (RLE)
Private Bus receive length error
DRDY# Protocol Error (FS2)
Asserted when a protocol error is found involving DRDY#, SBUSY# and DBUSY#.
Write Data Protocol Error (FS1)
Asserted on write protocol errors.
LEN# Protocol Error (FS0)
Asserted on mismatches of LEN# field and actual data transmitted.
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size:
Attribute:
Intel® 460GX Chipset Software Developer's Manual
32 bits
Read/Write to Clear