Register Descriptions; Access Mechanism - Intel 460GX Software Developer’s Manual

Register Descriptions

The 460GX chipset has both memory mapped and PCI configuration space mapped registers. The
460GX chipset supports access mechanism #1 as defined in the PCI specification. Two 32-bit
register locations (CONFIG_ADDRESS and CONFIG_DATA) are defined in the Itanium
processor's I/O space; I/O accesses to these registers are translated by the 460GX chipset into
appropriate PCI configuration cycles.
To access a configuration register in the 460GX chipset (or any other I/O device), software first
writes a value to the CONFIG_ADDRESS location consisting of the bus number, Device Number,
function number and register number. These writes are claimed and saved by the 460GX chipset.
Subsequent reads or writes to the CONFIG_DATA location result in the 460GX chipset using the
information stored in CONFIG_ADDRESS to deliver a PCI configuration read or write cycle to
the appropriate address on the appropriate PCI bus.
Upon reset, the 460GX chipset sets its internal configuration registers to predetermined default
states, representing the minimum feature set required to successfully bring up the system. It is
expected that the firmware will properly determine and program the optimal configuration settings.
The 460GX chipset implements a PCI-compatible configuration space for each PCI bus under the
PXBs, for each AGP bus under the GXB, and for each 460GX chipset component. Each
configuration space provides hardwired device identification, address range registers, operation
control registers, status and error registers. This chapter describes how the configuration spaces are
accessed, then provides detailed descriptions of each register.
2.1

Access Mechanism

The PCI specification defines two bus cycles to access PCI configuration space: Configuration
Read and Configuration Write. While memory and I/O spaces are supported by the microprocessor,
configuration space is not directly supported. The PCI specification defines two mechanisms to
access configuration space, Mechanism #1 and Mechanism #2. The 460GX chipset supports only
Mechanism #1.
Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at
location 0CF8h, and a data register (CONFIG_DATA) at location 0CFCh. Dword I/O Writes to the
configuration address are latched and held; they specify the PCI Bus Number, Device Number
within the bus, and Register Number within the device. Subsequent I/O reads and writes to the
configuration data location cause a configuration space access the register specified by the address
stored in the configuration address location.
Note: The AGP bus under the GXB looks like a standard PCI bus for configuration purposes. The term
xXB refers to the PXB, WXB, or GXB. In general, any reference to an access to PCI bus includes
accesses to an AGP bus.
Configuration space accesses are processed as follows:
•
If the SAC detects that the I/O request is a configuration access to its own configuration space,
it will service that request entirely within the SAC or the other chipset components. Reads
result in data being returned to the system bus.
•
If the SAC detects that the I/O request is a configuration access to a xXB configuration space,
it will forward the request to the appropriate xXB for servicing. The request is not forwarded
Intel® 460GX Chipset Software Developer's Manual
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