Intel 460GX Software Developer’s Manual page 142

AGP Subsystem
7.2.7.8 Retry/Disconnect Conditions
The GXB as a PCI target retries the initial data phase of inbound access when:
•
The read request is to an address that has already been accepted as a delayed transaction (i.e.
the request is already being serviced, but data has not arrived).
•
A write request has insufficient buffering in the gxb to allow it to be posted. (a full line is not
available for mwi).
•
The pci interface is locked from the host side.
•
No delayed read buffer is available.
The GXB as a target will issue a disconnect to a read when no more data is available (at the end of
the cacheline), or if linear addressing is not used. The GXB as a target will issue a disconnect to a
write when no more posting buffers are available, or when the write crosses a cacheline boundary.
7.2.7.9 Outbound Reads
Outbound reads are enqueued in the GXB. The GXB will hold up to four cache line reads at one
time. The GXB will continuously retry an outbound read until it completes successfully on the
AGP bus. Outbound posted writes must be allowed to pass the read(s) between retry attempts. PCI
2.2 ordering rules allow reads to pass each other. However, this is optional in the specification and
is not required to guarantee forward progress. For the GXB, outbound reads are done in order. If a
read is retried, then all other reads after it will wait until the first has completed.
7.2.7.10 Outbound Writes
Write Combining
The GXB optimizes outbound write performance by combining writes to sequential locations (if
enabled) into a single write burst on the AGP bus. This holds true for all memory attributes, not
just WC. The GXB only provides write combining; no collapsing or byte merging is performed.
The source of the transaction is not checked. Accesses from processors could be combined with
peer accesses.
The GXB will combine an access if the next data is valid at the head of the queue in time; this puts
a restriction on the size of requests that can be combined (if a request is too short the GXB does not
have time to look ahead). The GXB's write combining support is illustrated in
Notice that even if use of the Memory Write and Invalidate command is enabled, the GXB will not
terminate a burst that was started with a Memory Write command in order to switch to the Memory
Write Invalidate Command when it receives a full line. However, if a Memory Write Invalidate
burst has been started and the next sequential access is less than a line, the GXB must terminate and
switch to using the Memory Write command.
7-12
Table 7-4 shows some write combining examples.
Intel® 460GX Chipset Software Developer's Manual
Table 7-3.