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Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Datasheet

Supporting hyper-threading technology
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®
®
Intel
Pentium
4 Processors
570/571, 560/561, 550/551,
∆
540/541, 530/531 and 520/521
Supporting Hyper-Threading
1
Technology
Datasheet
On 90 nm Process in 775-land LGA Package and
Φ
®
supporting Intel
Extended Memory 64 Technology
May 2005
Document Number: 302351-004

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Summary of Contents for Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU

  • Page 1 ® ® Intel Pentium 4 Processors 570/571, 560/561, 550/551, ∆ 540/541, 530/531 and 520/521 Supporting Hyper-Threading Technology Datasheet On 90 nm Process in 775-land LGA Package and Φ ® supporting Intel Extended Memory 64 Technology May 2005 Document Number: 302351-004...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Itanium, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

  • Page 3: Table Of Contents

    Contents Contents Introduction............................ 11 Terminology ........................12 1.1.1 Processor Packaging Terminology ................ 12 References ......................... 13 Electrical Specifications ......................... 15 FSB and GTLREF....................... 15 Power and Ground Lands....................15 Decoupling Guidelines......................15 2.3.1 VCC Decoupling ....................16 2.3.2 FSB GTL+ Decoupling................... 16 2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ...........
  • Page 4 Contents 5.2.3 On-Demand Mode ....................81 5.2.4 PROCHOT# Signal....................82 5.2.5 THERMTRIP# Signal..................... 82 5.2.6 and Fan Speed Reduction..............82 CONTROL 5.2.7 Thermal Diode ....................... 83 Features ............................85 Power-On Configuration Options..................85 Clock Control and Low Power States ................. 85 6.2.1 Normal State......................
  • Page 5 3-4 Processor Package Drawing 3 ....................38 3-5 Processor Top-Side Marking Example ..................40 ® 3-6 Processor Top-Side Marking Example for Processors Supporting Intel EM64T ...... 41 3-7 Processor Land Coordinates (Top View)..................42 4-1 Landout Diagram (Top View – Left Side)..................44 4-2 Landout Diagram (Top View –...
  • Page 6 Contents Tables 1-1 References ..........................13 2-1 Core Frequency to FSB Multiplier Configuration ................ 16 2-2 Voltage Identification Definition ....................18 2-3 FSB Signal Groups........................21 2-4 Signal Characteristics ......................... 22 2-5 Signal Reference Voltages ......................22 2-6 BSEL[2:0] Frequency Table for BCLK[1:0] ................. 23 2-7 Processor DC Absolute Maximum Ratings ................

  • Page 7: Revision History

    Contents Revision History Revision No. Description Date of Release -001 • Initial release June 2004 • Added specifications for processor number 550 with PRB = 0 • Added support for Execute Disable Bit capability -002 September 2004 • Added Icc Enhanced Auto Halt specifications •...
  • Page 8 Contents Datasheet...
  • Page 9 Pentium 4 processor family supporting Hyper-Threading Technology (HT Technology) delivers Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel ® NetBurst microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance.
  • Page 10 Contents Datasheet...

  • Page 11: Introduction

    Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775LGA socket. The Pentium 4 processor in the 775-land package, like its predecessor, the Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.

  • Page 12: Terminology

    This feature can prevent some classes of viruses or worms that exploit buffer ® overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel Architecture Software Developer's Manual for more detailed information.

  • Page 13: References

    Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N–Z ® IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide http://developer.intel.com/ ® IA-32 Intel Architecture and Intel® Extended Memory 64 Software design/pentium4/ Developer's Manual Documentation Changes manuals/index_new.htm § Datasheet...
  • Page 14 Introduction Datasheet...

  • Page 15: Electrical Specifications

    GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to V . Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most GTL+ signals.

  • Page 16: Vcc Decoupling

    Electrical Specifications 2.3.1 Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR).

  • Page 17: Voltage Identification

    Electrical Specifications Voltage Identification The VID specification for the Pentium 4 processor in the 775-land package is supported by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor V pins.

  • Page 18: Voltage Identification Definition

    Electrical Specifications Table 2-2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID5 VID4 VID3 VID2 VID1 VID0 0.8375 1.2125 0.8500 1.2250 0.8625 1.2375 0.8750 1.2500 0.8875 1.2625 0.9000 1.2750 0.9125 1.2875 0.9250 1.3000 0.9375 1.3125 0.9500 1.3250 0.9625 1.3375 0.9750 1.3500...

  • Page 19: Phase Lock Loop (Pll) Power And Filter

    Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter and V are power sources required by the PLL clock generators for the Pentium 4 CCIOPLL processor in the 775-land package. Since these PLLs are analog, they require low noise power supplies for minimum jitter.

  • Page 20: Reserved, Unused, Fc And Testhi Signals

    Electrical Specifications Reserved, Unused, FC and TESTHI Signals All RESERVED signals must remain unconnected. Connection of these signals to V or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED signals.

  • Page 21: Fsb Signal Groups

    Electrical Specifications FSB Signal Groups The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output"...

  • Page 22: Gtl+ Asynchronous Signals

    Electrical Specifications NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

  • Page 23: Test Access Port (Tap) Connection

    Electrical Specifications Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and followed by any other components within the system.

  • Page 24: Absolute Maximum And Minimum Ratings

    Electrical Specifications 2.10 Absolute Maximum and Minimum Ratings Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the...

  • Page 25: Voltage And Current Specifications

    Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 1 of 2) Symbol Parameter Unit Notes VID range 1.200 — 1.425 Processor Number Core Frequency for 775_VR_CONFIG_04B processors Refer to Table 2-10 3, 4, 5, 6 570/571 3.80 GHZ (PRB = 1) Figure 2-3 560/561 3.60 GHz (PRB = 1)
  • Page 26 Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Unit Notes — — CC_VCCA CC FOR LANDS — — CC_VCCIOPLL I/O PLL CC FOR LAND µA for GTLREF — — CC_GTLREF NOTES: Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be up- dated with characterized data from silicon measurements at a later date.

  • Page 27: Vcc Static And Transient Tolerance For 775_Vr_Config_04A Processors

    Electrical Specifications Table 2-9. V Static and Transient Tolerance for 775_VR_CONFIG_04A Processors 1, 2, 3, 4 Voltage Deviation from VID Setting (V) Maximum Voltage Typical Voltage Minimum Voltage 1.70 mΩ 1.75 mΩ 1.80 mΩ 0.000 -0.025 -0.050 -0.009 -0.034 -0.059 -0.017 -0.043 -0.068...

  • Page 28: Vcc Static And Transient Tolerance For 775_Vr_Config_04A

    Electrical Specifications Figure 2-2. V Static and Transient Tolerance for 775_VR_CONFIG_04A Icc [A] VID - 0.000 VID - 0.025 Vcc Maximum VID - 0.050 VID - 0.075 Vcc Typical VID - 0.100 VID - 0.125 Vcc Minimum VID - 0.150 VID - 0.175 VID - 0.200 NOTES:...

  • Page 29: Vcc Static And Transient Tolerance For 775_Vr_Config_04B Processors

    Electrical Specifications Table 2-10. V Static and Transient Tolerance for 775_VR_CONFIG_04B Processors 1, 2, 3, 4 Voltage Deviation from VID Setting (V) Maximum Voltage Typical Voltage Minimum Voltage 1.30 mΩ 1.35 mΩ 1.40 mΩ 0.000 -0.019 -0.038 -0.007 -0.026 -0.045 -0.013 -0.033 -0.052...

  • Page 30: Vcc Static And Transient Tolerance For 775_Vr_Config_04B

    Electrical Specifications Figure 2-3. V Static and Transient Tolerance for 775_VR_CONFIG_04B Icc [A] VID - 0.000 VID - 0.019 VID - 0.038 Vcc Maximum VID - 0.057 VID - 0.076 VID - 0.095 Vcc Typical VID - 0.114 VID - 0.133 Vcc Minimum VID - 0.152 VID - 0.171...

  • Page 31: Gtl+ Asynchronous Signal Group Dc Specifications

    Electrical Specifications Table 2-11. GTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Unit Notes 2, 3 Input Low Voltage /2 – (0.10 * V 3, 4, 5, 6 Input High Voltage /2 + (0.10 * V 5, 6, 7 Output High Voltage 0.90*V /[(0.50*R TT_MIN...

  • Page 32: Pwrgood And Tap Signal Group Dc Specifications

    Electrical Specifications Table 2-13. PWRGOOD and TAP Signal Group DC Specifications 1, 2 Symbol Parameter Unit Notes Input Hysteresis Input low to high 0.5 * (V 0.5 * (V HYS_MIN) HYS_MAX threshold voltage Input high to low 0.5 * (V –...

  • Page 33: Vcc Overshoot Specification

    Electrical Specifications 2.12 Overshoot Specification The Pentium 4 processor in the 775-land package can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V is the maximum allowable overshoot voltage).

  • Page 34: Gtl+ Fsb Specifications

    915G/915GV/915P and 910GL Express chipset platforms use a pull-up resistor of 100 Ω and a pull-down resistor ® The Intel of 210 Ω. Contact your Intel representative for further details and documentation. These pull-ups are to V is the on-die termination resistance measured at V /2 of the GTL+ output driver.

  • Page 35: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications The Pentium 4 processor in the 775-land package is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.

  • Page 36: Processor Package Drawing 1

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing 1 Datasheet...

  • Page 37: Processor Package Drawing 2

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing 2 Datasheet...

  • Page 38: Processor Package Drawing 3

    Package Mechanical Specifications Figure 3-4. Processor Package Drawing 3 Datasheet...

  • Page 39: Processor Component Keep-Out Zones

    Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep- out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate.

  • Page 40: Package Insertion Specifications

    These diagrams aid in the identification of the Pentium 4 processor in the 775-land package. Figure 3-5. Processor Top-Side Marking Example Frequency/L2 Cache/Bus/ 775_VR_CONFIG_04x © ‘04 INTEL ® Pentium 4 S-Spec/Country of Assy 3.60GHz/1M/800/04B SLxxx [COO] [FPO]...

  • Page 41: Processor Land Coordinates

    Package Mechanical Specifications ® Figure 3-6. Processor Top-Side Marking Example for Processors Supporting Intel EM64T Processor Number/S-Spec/ Country of Assy © ‘04 INTEL ® Pentium 4 Frequency/L2 Cache/Bus/ 571 SLxxx [COO] 775_VR_CONFIG_04x 3.80GHZ/1M/800/04B [FPO] Unique Unit 2-D Matrix Mark Identifier...

  • Page 42: Processor Land Coordinates (Top View)

    Package Mechanical Specifications Figure 3-7. Processor Land Coordinates (Top View) Socket 775 Address / Common Quadrants Clock / Async Top View / Clocks Data § Datasheet...

  • Page 43: Land Listing And Signal Descriptions

    Land Listing and Signal Descriptions Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the Pentium 4 processor in the 775-land package. The landout footprint is shown in Figure 4-1 Figure 4-2.

  • Page 44: Landout Diagram (Top View - Left Side)

    Land Listing and Signal Descriptions Figure 4-1. Landout Diagram (Top View – Left Side) DP3# DP0# GTLREF BSEL1 DP2# DP1# _SEL BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD D43# D41#...

  • Page 45: Landout Diagram (Top View - Right Side)

    Land Listing and Signal Descriptions Figure 4-2. Landout Diagram (Top View – Right Side) VSS_MB_ VCC_MB_ VSS_ VCC_ FC16 REGULATION REGULATION SENSE SENSE FC12 VTTPWRGD FC11 VID2 VID0 VID3 VID1 VID5 PROCHOT# THERMDA RSVD VID4 ITP_CLK0 THERMDC A35# A34# ITP_CLK1 BPM0# BPM1# A33#...

  • Page 46: Alphabetical Land Assignments

    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Source Synch Input/Output BCLK1 Clock Input Source Synch Input/Output BINIT# Common Clock Input/Output Source Synch Input/Output BNR# Common Clock Input/Output...
  • Page 47 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D23# Source Synch Input/Output D63# Source Synch Input/Output D24# Source Synch Input/Output DBI0# Source Synch Input/Output D25#...
  • Page 48 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type ITP_CLK1 Input RESERVED LINT0 Asynch GTL+ Input RESERVED LINT1 Asynch GTL+ Input RESERVED LL_ID0...
  • Page 49 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AC26 Power/Other AG19 Power/Other AC27 Power/Other AG21 Power/Other AC28 Power/Other AG22 Power/Other AC29 Power/Other...
  • Page 50 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AK12 Power/Other AN12 Power/Other AK14 Power/Other AN14 Power/Other AK15 Power/Other AN15 Power/Other AK18 Power/Other...
  • Page 51 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 52 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AA24 Power/Other AF10 Power/Other AA25 Power/Other AF13 Power/Other AA26 Power/Other AF16 Power/Other AA27 Power/Other...
  • Page 53 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AJ23 Power/Other AM24 Power/Other AJ24 Power/Other AM27 Power/Other AJ27 Power/Other AM28 Power/Other AJ28 Power/Other...
  • Page 54 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 55 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...

  • Page 56: Numerical Land Assignment

    Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other RESERVED RS2# Common Clock Input Power/Other Source Synch Input/Output D53# Source Synch Input/Output Source Synch...
  • Page 57 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other RESERVED Power/Other RESERVED Power/Other Power/Other Power/Other D19# Source Synch Input/Output Power/Other D21# Source Synch...
  • Page 58 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Input D41# Source Synch Input/Output Power/Other D43# Source Synch Input/Output RSP# Common Clock...
  • Page 59 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other DP0# Common Clock Input/Output Power/Other DP3# Common Clock Input/Output Power/Other...
  • Page 60 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type TESTHI11 Power/Other Input Power/Other SMI# Asynch GTL+ Input Power/Other INIT# Asynch GTL+ Input Power/Other Power/Other...
  • Page 61 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type TESTHI1 Power/Other Input AA27 Power/Other Power/Other AA28 Power/Other A16# Source Synch Input/Output AA29 Power/Other...
  • Page 62 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type A22# Source Synch Input/Output Output Power/Other BPM4# Common Clock Input/Output Power/Other A28# Source Synch Input/Output...
  • Page 63 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AG12 Power/Other AH23 Power/Other AG13 Power/Other AH24 Power/Other AG14 Power/Other AH25 Power/Other AG15 Power/Other...
  • Page 64 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type VID4 Power/Other Output AL15 Power/Other Power/Other AL16 Power/Other RESERVED AL17 Power/Other Power/Other AL18 Power/Other...
  • Page 65 Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Table 4-2. Numerical Land Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AM27 Power/Other AN16 Power/Other AM28 Power/Other AN17 Power/Other AM29 Power/Other AN18 Power/Other AM30 Power/Other...

  • Page 66: Alphabetical Signals Reference

    Land Listing and Signal Descriptions Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub- phase 1 of the address phase, these signals transmit the address of a transaction.
  • Page 67 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
  • Page 68 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents.
  • Page 69 FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*- type floating-point error reporting.
  • Page 70 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 8) Name Type Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.
  • Page 71 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 8) Name Type Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Input/ PROCHOT# Thermal Control Circuit (TCC) has been activated, if enabled.
  • Page 72 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
  • Page 73 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 8) Name Type Description VID[5:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (V ). These are open drain signals that are driven by the processor and must be pulled up on the motherboard.
  • Page 74 Land Listing and Signal Descriptions Datasheet...

  • Page 75: Thermal Specifications And Design Considerations

    Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. ® For more information on designing a component level thermal solution, refer to the Intel ® Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines.

  • Page 76: Processor Thermal Specifications

    The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in...

  • Page 77: Thermal Profile For Processors With Prb = 1

    Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for Processors with PRB = 1 Power Maximum T Power Maximum T Power Maximum T Power Maximum T (°C) (°C) (°C) (°C) 44.0 51.5 59.0 66.5 44.5 52.0 59.5 67.0 45.0 52.5 60.0 67.5...

  • Page 78: Thermal Profile For Processors With Prb = 0

    Thermal Specifications and Design Considerations Table 5-3. Thermal Profile for Processors with PRB = 0 Power Maximum Tc Power Maximum Tc Power Maximum Tc (°C) (°C) (°C) 44.2 52.6 61.0 44.8 53.2 61.6 45.3 53.7 62.1 45.9 54.3 62.7 46.4 54.8 63.2 47.0...

  • Page 79: Thermal Metrology

    Intel recommends T thermal measurements should be made. For detailed guidelines on ® ® temperature measurement methodology, refer to the Intel Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines. Figure 5-3. Case Temperature (T...

  • Page 80: Thermal Monitor 2

    ® ® processor even when the TCC is active continuously. Refer to the Intel Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines for information on designing a thermal solution.

  • Page 81: On-Demand Mode

    Thermal Specifications and Design Considerations Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT# Time The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.

  • Page 82: Prochot# Signal

    Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software Developer's Manuals for specific register and programming details.

  • Page 83: Thermal Diode

    3.33 3.594 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Characterized at 75 °C. Not 100% tested. Specified by design characterization. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:...
  • Page 84 Thermal Specifications and Design Considerations Datasheet...

  • Page 85: Features

    Features Features Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor in the 775- land package samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1.

  • Page 86: Normal State

    (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information.

  • Page 87: Stop-Grant State

    Features Figure 6-1. Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Enhanced HALT or HALT State Normal State INIT#, BINIT#, INTR, NMI, SMI#, BCLK running Normal execution RESET#, FSB interrupts Snoops and interrupts allowed Snoop Snoop Event...

  • Page 88: Enhanced Halt Snoop Or Halt Snoop State, Grant Snoop State

    Features 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State.

  • Page 89: Boxed Processor Specifications

    Pentium 4 processor in the 775-land package. Note: Drawings in this section reflect only the specifications on the boxed Intel processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’...

  • Page 90: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium 4 processor on 90 nm process in the 775-land package. The boxed processor will be shipped with an unattached fan heatsink.

  • Page 91: Boxed Processor Fan Heatsink Weight

    The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the ® ® Intel Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines for details on the processor weight and heatsink requirements. 7.1.3...

  • Page 92: Boxed Processor Fan Heatsink Power Cable Connector Description

    Boxed Processor Specifications The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V to match the system board- mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.

  • Page 93: Thermal Specifications

    Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket R4.33 [110] Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.

  • Page 94: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

    Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View) Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View) Datasheet...

  • Page 95: Variable Speed Fan

    Boxed Processor Specifications 7.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.

  • Page 96: Fan Heatsink Power And Signal Specifications

    As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by...

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