Sid-Subsystem Id (Function 3); Intln-Interrupt Line Register (Function 3); Intpn-Interrupt Pin (Function 3); Host Configuration - Intel 460GX Software Developer’s Manual

14.2.9 SID–Subsystem ID (Function 3)
Address:
Default Value:
Attribute:
Bit
15:0
14.2.10 INTLN–Interrupt Line Register (Function 3)
Address Offset:
Default Value:
Attribute:
Software programs this register with interrupt information concerning the Power Management
module.
Bit
7:0
14.2.11 INTPN–Interrupt Pin (Function 3)
Address Offset:
Default Value:
Attribute:
This register indicates that PCI interrupt PIRQB# is used for the Power Management module.
Bit
7:3
2:0
14.2.12

Host Configuration

Address Offset:
Default Value:
Attribute:
Bit
7:2
1
0
Intel® 460GX Chipset Software Developer's Manual
2E-2Fh
0000h
Read only
Subsystem ID.
3Ch
00h
Read/Write
Interrupt Line. The value in this register has no affect on IFB hardware operations.
3Dh
02h
Read only
Reserved.
Serial Bus Module Interrupt Routing. This field is hardwired to 02h to indicate that PCI
interrupt pin PIRQB# is used.
40h
00h
Read/Write
Reserved.
SMI_EN: When this bit is set, any source of an SMB interrupt will instead be routed to generate
an SMI#. This bit will only take effect if the INTREN bit is set in I/O space.
HST_EN: When set, the SMB Host Controller interface is enabled to execute commands. The
HST_INT_EN bit needs to be enabled in order for the SMB Host Controller to interrupt or SMI#.
Additionally, the SMB Host Controller will not respond to any new requests until all interrupt
requests have been. The HST_EN bit does not affect the SMB Slave Port.
SM Bus Controller Configuration
Description
Description
Description
Description
14-5