Gxb - Intel 460GX Software Developer’s Manual

Register Descriptions
2.4.5

GXB

2.4.5.1 FERR_GXB
Function Number:
Address Offset:
Default Value:
Sticky:
These registers record the first error detected by the GXB. For the order to clear this register with
respect to the other GXB error registers.
Bits
7:3
2
1
0
2.4.5.2 FERR_PCI
Function Number:
Address Offset:
Default Value:
Sticky:
These registers record the first error detected in GPI.
Bits
7
6
5
4
3
2
1
0
2.4.5.3 FERR_AGP: First Error Status Register for AGP
Function Number:
Address Offset:
2-24
BFN+1
80h
00h
Yes
Description
reserved (0)
FERR_PCI bit asserted
FERR_AGP bit asserted
FERR_GART bit asserted
BFN+1
84h
00h each
Yes
Description
PCISTS Error Logged
This bit is asserted when an error, except for a master abort, has been logged in the PCI
Status register.
Non-Configuration Master Abort
This bit is asserted when a master abort occurs on any transaction other than a
configuration read or configuration write.
reported the same as a master abort - see PCISTS register
Discard Timer Expiration
15
This is the 2 clock timeout.
SERR# Observed
PERR# Observed
PCI Inbound Read Que Data Parity Error
Parity error detected as read data is retrieved from buffer.
PCI Outbound Write Que Data Parity Error
Parity error detected as write data is retrieved from buffer.
Illegal OB GART Access
Access may continue or abort, results undefined.
BFN+1
85h
Size:
Attribute:
Locked:
Size:
Attribute:
Locked:
Size:
Intel® 460GX Chipset Software Developer's Manual
8 bits
Read/Write Clear
No
8 bits
Read/Write Clear
No
8 bits