Pcists-Pci Device Status Register (Function 1); Classc-Class Code Register (Function 1) - Intel 460GX Software Developer’s Manual

12.2.4 PCISTS–PCI Device Status Register (Function 1)
Address Offset:
Default Value:
Attribute:
PCISTS is a 16-bit status register for the IDE interface Function. The register also indicates the
IFB's DEVSEL# signal timing.
Bit
15
14
13
12
11
10:9
8
7
6:0
12.2.5 CLASSC–Class Code Register (Function 1)
Address Offset:
Default Value:
Attribute:
This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface
for IFB PCI Function 1.
Bit
23:16
15:8
7:0
Intel® 460GX Chipset Software Developer's Manual
06–07h
0280h
Read/Write
Detected Parity Error. Read as 0.
SERR# Status. Read as 0.
Master-Abort Status (MAS)–R/WC. When the Bus Master IDE interface Function, as a master,
generates a master abort, MAS is set to a 1. Software sets MAS to 0 by writing a 1 to this bit.
Received Target-Abort Status (RTA)–R/WC. When the Bus Master IDE interface Function is a
master on the PCI Bus and receives a target abort, this bit is set to a 1. Software sets RTA to 0
by writing a 1 to this bit.
Signaled Target Abort Status (STA)–R/WC. This bit is set when the IFB IDE interface Function
is targeted with a transaction that the IFB terminates with a target abort. Software resets STA to
0 by writing a 1 to this bit.
DEVSEL# Timing Status (DEVT)–RO. For the IFB, DEVT=01 indicating medium timing for
DEVSEL# assertion when performing a positive decode. DEVSEL# timing does not include
configuration cycles.
Data Parity Detected (DPD). Read as 0.
Fast Back to back Capable (FBC)–RO. Hardwired to a 1.
Reserved.
09-0Bh
010180h
Read only
Base Class Code (BASEC). 01h=Mass storage device.
Sub-Class Code (SCC). 01h=IDE controller.
Programming Interface (PI). 80h=Capable of IDE bus master operation.
Description
Description
IDE Configuration
12-3