Intel 460GX Software Developer’s Manual page 40

Register Descriptions
2.4.2.26 SECF_D_FERR: Data on First System Bus SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data corresponding to the first SEC detected by system bus
interface in the SDC.
Bits
63:0
2.4.2.27 SECF_ECC_FERR: ECC on First System Bus SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the ECC checkbits corresponding to the first SEC detected by
system bus interface in the SDC.
Bits
7:0
2.4.2.28 SECF_TXINFO_FERR: TXINFO on First System Bus SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first SEC detected by system
bus interface in the SDC.
Bits
15:9
8:6
5:0
2.4.2.29 DEDF_D_FERR: Data on First System Bus DED
Bus CBN, Device Number:
Address Offset:
Default Value:
2-20
04h
E0-E7h
0
Description
DE - System Data of Error.
04h
E8h
00h
Description
ECC - ECC of Error.
04h
E9-EAh
00h
Description
reserved(0)
DC - Data Chunk of error.
ITID - ITID of error.
04h
F0-F7h
0
Size: 64 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 64 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Intel® 460GX Chipset Software Developer's Manual