Hot-Plug Features; Switch Change Serr Status; Power Fault Serr Status - Intel 460GX Software Developer’s Manual

11:8
7
6:2
1
0
8.1.18

Hot-Plug Features

Address Offset:
Default Value:
Definitions of each bit within this register are expected to be constant through the industry but are,
as of yet, undefined.
Bits
15:0
8.1.19

Switch Change SERR Status

Address Offset:
Default Value:
Bits
7:6
5:0
8.1.20

Power Fault SERR Status

Address Offset:
Default Value:
Bits
7:6
5:0
Intel® 460GX Chipset Software Developer's Manual
reserved(0)
Enable PCI Configuration Space Access to Hot-Plug Registers. Enables IHPC memory-
mapped register access through the index register (configuration offset 50h) and data port
(configuration offset 54h).
reserved (0)
reserved (1)
On / Off Busy (OOBS) status. Read Only. Same as bit 24 of the memory-mapped Hot-
Plug Miscellaneous register.
44h-45
0000h
Description
reserved (0)
48h
00h
Description
reserved (0)
Switch Change SERR Status. Slot F is MSB. Slot A is LSB. Similar to the Power Fault
SERR status register, but applicable to switch changes when the switch interrupt redirect
bit for a slot is set and the associated interrupt mask bit is logic 0. Unlike the Power Fault
SERR status register, clearing this bit will also clear the associated interrupt.
49h
00h
Description
reserved.
Power Fault SERR Status. If the power fault function enable bit and the SERR on power
fault bit are both set, then these six bits will indicate (by a logic 1, one for each slot) if a
power fault has occurred while a slot was connected to the bus or clock. Slot F is MSB.
Slot A is LSB. These bits can be cleared by writing a logic 1 to the appropriate position.
This register does not effect PCI interrupts.
WXB Hot-Plug
Size: 16 bits
Attribute: Read Only
Size: 8 bits
Attribute: Partial Read/Write
Size: 8 bits
Attribute: Partial Read/Write
8-9