Intel 460GX Software Developer’s Manual page 211

Bit
7:5
4
3
2
1
0
11.2.2.2 Icw2–Initialization Command Word 2 Register (I/O)
I/O Address:
Default Value:
Attribute:
ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt
vector address.
Bit
7:3
2:0
11.2.2.3 Icw3–Initialization Command Word 3 Register (I/O)
I/O Address:
Default Value:
Attribute:
The meaning of ICW3 differs between CNTRL-1 and CNTRL-2. On CNTRL-1, the master
controller, ICW3 indicates which CNTRL-1 IRQ line physically connects the INTR output of
CNTRL-2 to CNTRL-1.
Bit
7:3
2
1:0
Intel® 460GX Chipset Software Developer's Manual
ICW/OCW select. These bits should be 000 when programming the IFB.
ICW/OCW select. Bit 4 must be a 1 to select ICW1. After the fixed initialization sequence to
ICW1, ICW2, ICW3, and ICW4, the controller base address is used to write to OCW2 and
OCW3. Bit 4 is a 0 on writes to these registers. A 1 on this bit at any time will force the interrupt
controller to interpret the write as an ICW1. The controller will then expect to see ICW2, ICW3,
and ICW4.
Edge/Level Bank Select (LTIM). This bit is disabled. Its Function is replaced by the Edge/
Level Triggered Control (ELCR) Registers.
ADI. Ignored for the IFB. This bit should be programmed to '0'.
Single or Cascade (SNGL). This bit must be programmed to a 0.
ICW4 Write Required (IC4). This bit must be set to a 1.
INT CNTRL-1–021h; INT CNTRL-2–0A1h
All bits undefined
Write Only
Interrupt Vector Base Address. Bits [7:3] define the base address in the interrupt vector table
for the interrupt routines associated with each interrupt request level input.
Interrupt Request Level. Must be programmed to all 0s.
INT CNTRL-1–021h
All bits undefined
Write Only
Reserved. Must be programmed to all 0s.
Cascaded Mode Enable. This bit must be programmed to 1 selecting cascade mode.
Reserved. Must be programmed to all 0s.
LPC/FWH Interface Configuration
Description
Description
Description
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