Legal And Illegal Address Disposition; Address Disposition - Intel 460GX Software Developer’s Manual

System Address Map
4.4

Legal and Illegal Address Disposition

Below is the disposition of addresses done by the Bus Interface Unit (BIU).
Table 4-1. Address Disposition
Address Range
0-07FFFFh
080000h-09FFFFh
0A0000h-0BFFFFh
0C0000h-0EFFFFh
(divided into 12 regions of 4k
bytes)
0F_0000h-0F_FFFFh
10_0000h - PCIS[7]
PCIS[7] - FDFF_FFFFh
FE00_0000h-FE1F_FFFFh
FE20_0000h-FE3F_FFFFh
FE40_0000h-FE5F_FFFFh
FE60_0000h to FEBF_FFFFh
FEC0_0000 to FECF_FFFFh
FED0_0000h to FEDF_FFFFh
FEE0_0000h to FEEF_FFFFh
4-8
Outbound Inbound
DRAM DRAM
DRAM DRAM
PCI0a unclaimed
DRAM DRAM
PCIx unclaimed
DRAM DRAM
PCI0a unclaimed
DRAM DRAM
PCI0a unclaimed
DRAM DRAM
PCIx PCIx
undefined undefined
Expander port- Expander port
2 or PCI0A 2 or PCI0A
undefined
undefined
Config unit or Config unit or
PCI-0a PCI-0a
PCI x unclaimed
PCI 0a or PXB will
dropped forward IB and
mark it to
memory.
Interrupt interrupt for IB
Transaction; write, PCI-0a
Reads sent to for read
PCI 0a, writes
dropped
Intel® 460GX Chipset Software Developer's Manual
Dest. Decision
MAR=11 or (Read and MAR= 01 and
no system bus LOCK#) or (Write and
MAR = 10)
MAR=00 or (Read and MAR=01 and
system bus LOCK#) or (Read and
MAR=10) or (Write and MAR=01)
VGASE=0
VGASE=1
MAR=11 or (Read and MAR= 01 and
no LOCK#) or (Write and MAR = 10)
MAR=00 or (Read and MAR=01 and
LOCK#) or (Read and MAR=10) or
(Write and MAR=01)
MAR=11 or (Read and MAR= 01 and
no LOCK#) or (Write and MAR = 10)
MAR=00 or (Read and MAR=01 and
LOCK#) or (Read and MAR=10) or
(Write and MAR=01)
PXB uses LXGB instead of PCIS[7]
PCIS register determines target PCI
bus
On PCI if
MMBASE<=address<=MMT, then not
claimed. GXB: unclaimed
This region is reserved.
If DEVNPRES[14]=0, send to
Expander port 2, else send to PCI-0a
This region is reserved.
If <=8B then: if one of defined
registers read or write value, if not
then return all 1's or terminate writes.
If >8B, then send to PCI-0a. NOTE:
Locks to this range are forbidden and
will hang the system
SAR, IOABASE (PXB)
Reads are sent to PCI-0a for master
abort. Writes get No-Data response
and are dropped
Reads are sent to PCI-0a for master
abort. IB writes are turned to
interrupts. OB writes get No-Data
response and are dropped