Data Flow Errors; Sac Error Flow On Data - Intel 460GX Software Developer’s Manual

Data Integrity and Error Handling
Take the case where processor 1 reads a line from memory and there are no errors, and then does a
write into its cache. Later processor 2 does a read, getting an IWB. The SAC starts a speculative
read for the line before seeing the HITM#. If the data in DRAM has a 2x error on this read the
SDC data buffer will be marked as having a 2x error on this line. In this case, assuming the
speculative read is done (in some cases the HITM# is seen before the memory cycle is attempted,
so no speculative read is done), the IWB data that is written back into memory will be poisoned.
6.9

Data Flow Errors

Figure 6-1
DRAM errors for either single-bit (S) or double-bit (D) fails. The SDC will never signal that an
error was fatal (causing BINIT#). The processor will handle data that it receives with bad ECC.
The memory will have bad ECC written to it, if incoming data is bad. Data to the SAC will be
handled by the SAC itself. Either the SAC will BINIT# on seeing bad data or it will pass it on to
the xXB via an Expander port.
Figure 6-1. SAC Error Flow on Data
Check parity on
header and data.
Check for HF.
6-14
and Figure 6-2 show the data flow and errors that are checked. The SDC will report
System Bus
Address parity.
Request parity
.
Bus protocol checking
1 parity per 18 bits (16 data and 2 BE)
From
BIU
1 parity, 16 data,
2b BE
2 BE
From
BIU
Expander: From xXB
1 parity per 16 bits (16 data)
16b data,
1Parity
Generate
parity as DP xor
Check outgoing
BE0 xor BE1, not
parity from data
18-way XOR
buffer.
Expander: To xXB
Intel® 460GX Chipset Software Developer's Manual
ITID
Check parity.
RETIREMENT
BUS
Check parity.
.
Pass data with
good/bad parity to
TO
SDC or Expander (peer).
No checking done.
SDC
68b bus
1 parity per
16b of data
Pass data from SDC
From
to Expander bus with
SDC
good/bad parity.
No checking done.