Intel 460GX Software Developer’s Manual page 11

7-4
7-5
Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
4-1
5-1
5-2
5-3
5-4
6-1
6-2
6-3
6-4
6-5
7-1
7-2
7-3
7-4
7-5
8-1
8-2
9-1
9-2
9-3
9-4
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
Intel® 460GX Chipset System Software Developer's Manual
GART Entry Format for 4 MB Pages..................................................................7-3
GART SRAM Timings ........................................................................................7-5
Intel® 460GX Chipset Components ...................................................................1-2
Device Mapping on Bus CBN.............................................................................2-2
Memory-Mapped Register Summary ...............................................................2-45
I/O Select Register Format...............................................................................2-45
I/O Window Register Format ............................................................................2-46
(x)APIC EOI Register Format...........................................................................2-46
Memory-mapped Register Summary ...............................................................2-47
I/O APIC ID Register Format............................................................................2-49
I/O (x)APIC Version Register Format ...............................................................2-49
I/O (x)APIC Arbitration ID Register Format ......................................................2-50
I/O (x)APIC RTE Format ..................................................................................2-50
Address Disposition............................................................................................4-8
General Memory Characteristics........................................................................5-1
Minimum/Maximum Memory Size per Configuration..........................................5-3
Required DRAM Parameters..............................................................................5-6
Scrubbing Time ..................................................................................................5-7
Error Cases ......................................................................................................6-16
List of WXB Error Sources Selectively Routable to XBINIT#, SERR_OUT#,
and P(A/B)INTRQ#...........................................................................................6-27
Supported Error Escalation to XBINIT#............................................................6-27
Supported Error Escalation to SERR_OUT#....................................................6-28
Supported Error Escalation to P(A/B)INTRQ# .................................................6-28
Coherency for AGP/PCI Streams.......................................................................7-8
Delayed Read Matching Criteria ......................................................................7-11
Burst Write Combining Modes..........................................................................7-13
Burst Write Combining Examples with 3 Writes in 1X Transfer Mode .............7-13
Bandwidth Estimates for Various Request Sizes .............................................7-14
IHPC Configuration Register Space...................................................................8-2
IHPC Memor Mapped Register Space .............................................................8-11
PCI Configuration Registers-Function 0(PCI to LPC/FWH Interface Bridge) ....9-1
PCI Configuration Registers-Function 1 (IDE Interface)....................................9-3
PCI Configuration Registers-Function 2 (USB Interface) ..................................9-4
PCI Configuration Registers-Function 3 (SMBus Controller Interface) .............9-5
Identify Device Information Used for Determining Drive Capabilities...............10-3
Identify Device Information Used for Determining Ultra DMA
Drive Capabilities .............................................................................................10-5
Identify Device Information Used for Determining Multi/Single Word DMA
Drive Capabilities .............................................................................................10-6
Drive Multi Word DMA/Single Word DMA Capability as a Function
of Cycle Time ...................................................................................................10-7
Identify Device Information Used for Determining PIO Drive Capabilities........10-8
Drive PIO Capability as a Function of Cycle Time ...........................................10-8
IFB Drive Mode Based on DMA/PIO Capabilities ............................................10-9
IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation ...............10-10
DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed............10-11
xi